| developer | 4d81931 | 2021-07-05 20:42:09 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2021, MediaTek Inc. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef PLAT_DFD_H |
| 8 | #define PLAT_DFD_H |
| 9 | |
| 10 | #include <arch_helpers.h> |
| 11 | #include <lib/mmio.h> |
| 12 | #include <platform_def.h> |
| 13 | |
| 14 | #define sync_writel(addr, val) do { mmio_write_32((addr), (val)); \ |
| 15 | dsbsy(); \ |
| 16 | } while (0) |
| 17 | |
| 18 | #define PLAT_MTK_DFD_SETUP_MAGIC (0x99716150) |
| 19 | #define PLAT_MTK_DFD_READ_MAGIC (0x99716151) |
| 20 | #define PLAT_MTK_DFD_WRITE_MAGIC (0x99716152) |
| 21 | |
| 22 | #define MCU_BIU_BASE (MCUCFG_BASE) |
| 23 | #define MISC1_CFG_BASE (MCU_BIU_BASE + 0xE040) |
| 24 | #define DFD_INTERNAL_CTL (MISC1_CFG_BASE + 0x00) |
| 25 | #define DFD_INTERNAL_PWR_ON (MISC1_CFG_BASE + 0x08) |
| 26 | #define DFD_CHAIN_LENGTH0 (MISC1_CFG_BASE + 0x0C) |
| 27 | #define DFD_INTERNAL_SHIFT_CLK_RATIO (MISC1_CFG_BASE + 0x10) |
| 28 | #define DFD_CHAIN_LENGTH1 (MISC1_CFG_BASE + 0x1C) |
| 29 | #define DFD_CHAIN_LENGTH2 (MISC1_CFG_BASE + 0x20) |
| 30 | #define DFD_CHAIN_LENGTH3 (MISC1_CFG_BASE + 0x24) |
| 31 | #define DFD_INTERNAL_TEST_SO_0 (MISC1_CFG_BASE + 0x28) |
| 32 | #define DFD_INTERNAL_NUM_OF_TEST_SO_GROUP (MISC1_CFG_BASE + 0x30) |
| 33 | #define DFD_INTERNAL_TEST_SO_OVER_64 (MISC1_CFG_BASE + 0x34) |
| 34 | #define DFD_V30_CTL (MISC1_CFG_BASE + 0x48) |
| 35 | #define DFD_V30_BASE_ADDR (MISC1_CFG_BASE + 0x4C) |
| 36 | #define DFD_POWER_CTL (MISC1_CFG_BASE + 0x50) |
| 37 | #define DFD_TEST_SI_0 (MISC1_CFG_BASE + 0x58) |
| 38 | #define DFD_TEST_SI_1 (MISC1_CFG_BASE + 0x5C) |
| 39 | #define DFD_CLEAN_STATUS (MISC1_CFG_BASE + 0x60) |
| 40 | #define DFD_TEST_SI_2 (MISC1_CFG_BASE + 0x1D8) |
| 41 | #define DFD_TEST_SI_3 (MISC1_CFG_BASE + 0x1DC) |
| 42 | #define DFD_HW_TRIGGER_MASK (MISC1_CFG_BASE + 0xBC) |
| 43 | |
| 44 | #define DFD_V35_ENALBE (MCU_BIU_BASE + 0xE0A8) |
| 45 | #define DFD_V35_TAP_NUMBER (MCU_BIU_BASE + 0xE0AC) |
| 46 | #define DFD_V35_TAP_EN (MCU_BIU_BASE + 0xE0B0) |
| 47 | #define DFD_V35_CTL (MCU_BIU_BASE + 0xE0B4) |
| 48 | #define DFD_V35_SEQ0_0 (MCU_BIU_BASE + 0xE0C0) |
| 49 | #define DFD_V35_SEQ0_1 (MCU_BIU_BASE + 0xE0C4) |
| 50 | |
| 51 | #define DFD_O_PROTECT_EN_REG (0x10001220) |
| 52 | #define DFD_O_INTRF_MCU_PWR_CTL_MASK (0x10001A3C) |
| 53 | #define DFD_O_SET_BASEADDR_REG (0x10043034) |
| 54 | |
| 55 | #define DFD_CACHE_DUMP_ENABLE 1U |
| 56 | #define DFD_PARITY_ERR_TRIGGER 2U |
| 57 | |
| 58 | #define DFD_TEST_SI_0_CACHE_DIS_VAL (0x1E000202) |
| 59 | #define DFD_TEST_SI_0_CACHE_EN_VAL (0x1E000002) |
| 60 | #define DFD_TEST_SI_1_VAL (0x20408100) |
| 61 | #define DFD_TEST_SI_2_VAL (0x10101000) |
| 62 | #define DFD_TEST_SI_3_VAL (0x00000010) |
| 63 | #define DFD_V35_TAP_EN_VAL (0x43FF) |
| 64 | #define DFD_V35_SEQ0_0_VAL (0x63668820) |
| 65 | |
| 66 | void dfd_resume(void); |
| 67 | uint64_t dfd_smc_dispatcher(uint64_t arg0, uint64_t arg1, |
| 68 | uint64_t arg2, uint64_t arg3); |
| 69 | |
| 70 | #endif /* PLAT_DFD_H */ |