| Jayanth Dodderi Chidanand | 37de916 | 2021-12-07 17:20:10 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2022, Arm Limited. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
| 8 | #include <asm_macros.S> |
| 9 | #include <common/bl_common.h> |
| 10 | #include <neoverse_poseidon.h> |
| 11 | #include <cpu_macros.S> |
| 12 | #include <plat_macros.S> |
| 13 | |
| 14 | /* Hardware handled coherency */ |
| 15 | #if HW_ASSISTED_COHERENCY == 0 |
| 16 | #error "Neoverse Poseidon must be compiled with HW_ASSISTED_COHERENCY enabled" |
| 17 | #endif |
| 18 | |
| 19 | /* 64-bit only core */ |
| 20 | #if CTX_INCLUDE_AARCH32_REGS == 1 |
| 21 | #error "Neoverse Poseidon supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" |
| 22 | #endif |
| 23 | |
| 24 | /* --------------------------------------------- |
| 25 | * HW will do the cache maintenance while powering down |
| 26 | * --------------------------------------------- |
| 27 | */ |
| 28 | func neoverse_poseidon_core_pwr_dwn |
| 29 | /* --------------------------------------------- |
| 30 | * Enable CPU power down bit in power control register |
| 31 | * --------------------------------------------- |
| 32 | */ |
| 33 | mrs x0, NEOVERSE_POSEIDON_CPUPWRCTLR_EL1 |
| 34 | orr x0, x0, #NEOVERSE_POSEIDON_CPUPWRCTLR_EL1_CORE_PWRDN_BIT |
| 35 | msr NEOVERSE_POSEIDON_CPUPWRCTLR_EL1, x0 |
| 36 | isb |
| 37 | ret |
| 38 | endfunc neoverse_poseidon_core_pwr_dwn |
| 39 | |
| 40 | #if REPORT_ERRATA |
| 41 | /* |
| 42 | * Errata printing function for Neoverse Poseidon. Must follow AAPCS. |
| 43 | */ |
| 44 | func neoverse_poseidon_errata_report |
| 45 | ret |
| 46 | endfunc neoverse_poseidon_errata_report |
| 47 | #endif |
| 48 | |
| 49 | func neoverse_poseidon_reset_func |
| 50 | /* Disable speculative loads */ |
| 51 | msr SSBS, xzr |
| 52 | isb |
| 53 | ret |
| 54 | endfunc neoverse_poseidon_reset_func |
| 55 | |
| 56 | /* --------------------------------------------- |
| 57 | * This function provides Neoverse-Poseidon specific |
| 58 | * register information for crash reporting. |
| 59 | * It needs to return with x6 pointing to |
| 60 | * a list of register names in ascii and |
| 61 | * x8 - x15 having values of registers to be |
| 62 | * reported. |
| 63 | * --------------------------------------------- |
| 64 | */ |
| 65 | .section .rodata.neoverse_poseidon_regs, "aS" |
| 66 | neoverse_poseidon_regs: /* The ascii list of register names to be reported */ |
| 67 | .asciz "cpuectlr_el1", "" |
| 68 | |
| 69 | func neoverse_poseidon_cpu_reg_dump |
| 70 | adr x6, neoverse_poseidon_regs |
| 71 | mrs x8, NEOVERSE_POSEIDON_CPUECTLR_EL1 |
| 72 | ret |
| 73 | endfunc neoverse_poseidon_cpu_reg_dump |
| 74 | |
| 75 | declare_cpu_ops neoverse_poseidon, NEOVERSE_POSEIDON_MIDR, \ |
| 76 | neoverse_poseidon_reset_func, \ |
| 77 | neoverse_poseidon_core_pwr_dwn |