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Nariman Poushin0ece80f2018-02-26 06:52:04 +00001/*
Arvind Ram Prakash11b9b492022-11-22 14:41:00 -06002 * Copyright (c) 2018-2023, Arm Limited and Contributors. All rights reserved.
Nariman Poushin0ece80f2018-02-26 06:52:04 +00003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00007#include <assert.h>
8
9#include <platform_def.h>
10
11#include <common/bl_common.h>
12#include <common/debug.h>
13#include <drivers/arm/ccn.h>
Antonio Nino Diazbd7b7402019-01-25 14:30:04 +000014#include <plat/arm/common/plat_arm.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000015#include <plat/common/platform.h>
Aditya Angadi20b48412019-04-16 11:29:14 +053016#include <drivers/arm/sbsa.h>
17#include <sgi_base_platform_def.h>
Olivier Deprez21cf3602020-07-30 17:18:33 +020018
19#if SPM_MM
Paul Beesley45f40282019-10-15 10:57:42 +000020#include <services/spm_mm_partition.h>
Olivier Deprez21cf3602020-07-30 17:18:33 +020021#endif
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000022
Nariman Poushin0ece80f2018-02-26 06:52:04 +000023#define SGI_MAP_FLASH0_RO MAP_REGION_FLAT(V2M_FLASH0_BASE,\
24 V2M_FLASH0_SIZE, \
25 MT_DEVICE | MT_RO | MT_SECURE)
26/*
27 * Table of regions for different BL stages to map using the MMU.
28 * This doesn't include Trusted RAM as the 'mem_layout' argument passed to
29 * arm_configure_mmu_elx() will give the available subset of that.
30 *
31 * Replace or extend the below regions as required
32 */
33#if IMAGE_BL1
34const mmap_region_t plat_arm_mmap[] = {
35 ARM_MAP_SHARED_RAM,
36 SGI_MAP_FLASH0_RO,
37 CSS_SGI_MAP_DEVICE,
38 SOC_CSS_MAP_DEVICE,
39 {0}
40};
41#endif
42#if IMAGE_BL2
43const mmap_region_t plat_arm_mmap[] = {
44 ARM_MAP_SHARED_RAM,
45 SGI_MAP_FLASH0_RO,
Sami Mujawara4f315c2020-04-30 15:50:34 +010046#ifdef PLAT_ARM_MEM_PROT_ADDR
47 ARM_V2M_MAP_MEM_PROTECT,
48#endif
Nariman Poushin0ece80f2018-02-26 06:52:04 +000049 CSS_SGI_MAP_DEVICE,
50 SOC_CSS_MAP_DEVICE,
51 ARM_MAP_NS_DRAM1,
Aditya Angadica14fb82021-02-17 18:39:32 +053052#if CSS_SGI_CHIP_COUNT > 1
53 CSS_SGI_MAP_DEVICE_REMOTE_CHIP(1),
54#endif
55#if CSS_SGI_CHIP_COUNT > 2
56 CSS_SGI_MAP_DEVICE_REMOTE_CHIP(2),
57#endif
58#if CSS_SGI_CHIP_COUNT > 3
59 CSS_SGI_MAP_DEVICE_REMOTE_CHIP(3),
60#endif
Nariman Poushin0ece80f2018-02-26 06:52:04 +000061#if ARM_BL31_IN_DRAM
62 ARM_MAP_BL31_SEC_DRAM,
63#endif
Paul Beesleyfe975b42019-09-16 11:29:03 +000064#if SPM_MM
Sughosh Ganue1579e02018-05-16 17:19:56 +053065 ARM_SP_IMAGE_MMAP,
66#endif
Arvind Ram Prakash11b9b492022-11-22 14:41:00 -060067#if TRUSTED_BOARD_BOOT && !RESET_TO_BL2
John Tsichritzis0c6ee742018-08-22 12:36:37 +010068 ARM_MAP_BL1_RW,
69#endif
Nariman Poushin0ece80f2018-02-26 06:52:04 +000070 {0}
71};
72#endif
73#if IMAGE_BL31
74const mmap_region_t plat_arm_mmap[] = {
75 ARM_MAP_SHARED_RAM,
76 V2M_MAP_IOFPGA,
77 CSS_SGI_MAP_DEVICE,
Sami Mujawara4f315c2020-04-30 15:50:34 +010078#ifdef PLAT_ARM_MEM_PROT_ADDR
79 ARM_V2M_MAP_MEM_PROTECT,
80#endif
Nariman Poushin0ece80f2018-02-26 06:52:04 +000081 SOC_CSS_MAP_DEVICE,
Paul Beesleyfe975b42019-09-16 11:29:03 +000082#if SPM_MM
Sughosh Ganue1579e02018-05-16 17:19:56 +053083 ARM_SPM_BUF_EL3_MMAP,
84#endif
Nariman Poushin0ece80f2018-02-26 06:52:04 +000085 {0}
86};
Sughosh Ganue1579e02018-05-16 17:19:56 +053087
Paul Beesleyfe975b42019-09-16 11:29:03 +000088#if SPM_MM && defined(IMAGE_BL31)
Sughosh Ganue1579e02018-05-16 17:19:56 +053089const mmap_region_t plat_arm_secure_partition_mmap[] = {
Thomas Abrahame4030c02021-02-15 14:14:59 +053090 PLAT_ARM_SECURE_MAP_SYSTEMREG,
91 PLAT_ARM_SECURE_MAP_NOR2,
Rohit Mathew9c07f602021-12-13 15:33:04 +000092 SOC_PLATFORM_SECURE_UART,
Sughosh Ganue1579e02018-05-16 17:19:56 +053093 PLAT_ARM_SECURE_MAP_DEVICE,
94 ARM_SP_IMAGE_MMAP,
95 ARM_SP_IMAGE_NS_BUF_MMAP,
Thomas Abrahama0aea1a2021-02-16 11:36:00 +053096#if RAS_EXTENSION
97 CSS_SGI_SP_CPER_BUF_MMAP,
98#endif
Sughosh Ganue1579e02018-05-16 17:19:56 +053099 ARM_SP_IMAGE_RW_MMAP,
100 ARM_SPM_BUF_EL0_MMAP,
101 {0}
102};
Paul Beesleyfe975b42019-09-16 11:29:03 +0000103#endif /* SPM_MM && defined(IMAGE_BL31) */
Nariman Poushin0ece80f2018-02-26 06:52:04 +0000104#endif
105
106ARM_CASSERT_MMAP
Sughosh Ganue1579e02018-05-16 17:19:56 +0530107
Paul Beesleyfe975b42019-09-16 11:29:03 +0000108#if SPM_MM && defined(IMAGE_BL31)
Sughosh Ganue1579e02018-05-16 17:19:56 +0530109/*
110 * Boot information passed to a secure partition during initialisation. Linear
111 * indices in MP information will be filled at runtime.
112 */
Paul Beesley45f40282019-10-15 10:57:42 +0000113static spm_mm_mp_info_t sp_mp_info[] = {
Sughosh Ganue1579e02018-05-16 17:19:56 +0530114 [0] = {0x81000000, 0},
115 [1] = {0x81000100, 0},
116 [2] = {0x81000200, 0},
117 [3] = {0x81000300, 0},
118 [4] = {0x81010000, 0},
119 [5] = {0x81010100, 0},
120 [6] = {0x81010200, 0},
121 [7] = {0x81010300, 0},
122};
123
Paul Beesley45f40282019-10-15 10:57:42 +0000124const spm_mm_boot_info_t plat_arm_secure_partition_boot_info = {
Sughosh Ganue1579e02018-05-16 17:19:56 +0530125 .h.type = PARAM_SP_IMAGE_BOOT_INFO,
126 .h.version = VERSION_1,
Paul Beesley45f40282019-10-15 10:57:42 +0000127 .h.size = sizeof(spm_mm_boot_info_t),
Sughosh Ganue1579e02018-05-16 17:19:56 +0530128 .h.attr = 0,
129 .sp_mem_base = ARM_SP_IMAGE_BASE,
130 .sp_mem_limit = ARM_SP_IMAGE_LIMIT,
131 .sp_image_base = ARM_SP_IMAGE_BASE,
132 .sp_stack_base = PLAT_SP_IMAGE_STACK_BASE,
133 .sp_heap_base = ARM_SP_IMAGE_HEAP_BASE,
Ard Biesheuvel8b034fc2018-12-29 19:43:21 +0100134 .sp_ns_comm_buf_base = PLAT_SP_IMAGE_NS_BUF_BASE,
Sughosh Ganue1579e02018-05-16 17:19:56 +0530135 .sp_shared_buf_base = PLAT_SPM_BUF_BASE,
136 .sp_image_size = ARM_SP_IMAGE_SIZE,
137 .sp_pcpu_stack_size = PLAT_SP_IMAGE_STACK_PCPU_SIZE,
138 .sp_heap_size = ARM_SP_IMAGE_HEAP_SIZE,
Ard Biesheuvel8b034fc2018-12-29 19:43:21 +0100139 .sp_ns_comm_buf_size = PLAT_SP_IMAGE_NS_BUF_SIZE,
Sughosh Ganue1579e02018-05-16 17:19:56 +0530140 .sp_shared_buf_size = PLAT_SPM_BUF_SIZE,
141 .num_sp_mem_regions = ARM_SP_IMAGE_NUM_MEM_REGIONS,
142 .num_cpus = PLATFORM_CORE_COUNT,
143 .mp_info = &sp_mp_info[0],
144};
145
146const struct mmap_region *plat_get_secure_partition_mmap(void *cookie)
147{
148 return plat_arm_secure_partition_mmap;
149}
150
Paul Beesley45f40282019-10-15 10:57:42 +0000151const struct spm_mm_boot_info *plat_get_secure_partition_boot_info(
Sughosh Ganue1579e02018-05-16 17:19:56 +0530152 void *cookie)
153{
154 return &plat_arm_secure_partition_boot_info;
155}
Paul Beesleyfe975b42019-09-16 11:29:03 +0000156#endif /* SPM_MM && defined(IMAGE_BL31) */
John Tsichritzis0c6ee742018-08-22 12:36:37 +0100157
Antonio Nino Diaz9b759862018-09-25 11:38:18 +0100158#if TRUSTED_BOARD_BOOT
John Tsichritzis0c6ee742018-08-22 12:36:37 +0100159int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
160{
161 assert(heap_addr != NULL);
162 assert(heap_size != NULL);
163
164 return arm_get_mbedtls_heap(heap_addr, heap_size);
165}
166#endif
Aditya Angadi20b48412019-04-16 11:29:14 +0530167
168void plat_arm_secure_wdt_start(void)
169{
170 sbsa_wdog_start(SBSA_SECURE_WDOG_BASE, SBSA_SECURE_WDOG_TIMEOUT);
171}
172
173void plat_arm_secure_wdt_stop(void)
174{
175 sbsa_wdog_stop(SBSA_SECURE_WDOG_BASE);
176}