| johpow01 | aef12f2 | 2020-10-15 13:40:04 -0500 | [diff] [blame] | 1 | /* |
| Bipin Ravi | 32464ba | 2022-05-06 16:02:30 -0500 | [diff] [blame] | 2 | * Copyright (c) 2021-2022, Arm Limited. All rights reserved. |
| johpow01 | aef12f2 | 2020-10-15 13:40:04 -0500 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef CORTEX_MAKALU_H |
| 8 | #define CORTEX_MAKALU_H |
| 9 | |
| 10 | #define CORTEX_MAKALU_MIDR U(0x410FD4D0) |
| 11 | |
| Bipin Ravi | 32464ba | 2022-05-06 16:02:30 -0500 | [diff] [blame] | 12 | /* Cortex Makalu loop count for CVE-2022-23960 mitigation */ |
| 13 | #define CORTEX_MAKALU_BHB_LOOP_COUNT U(38) |
| 14 | |
| johpow01 | aef12f2 | 2020-10-15 13:40:04 -0500 | [diff] [blame] | 15 | /******************************************************************************* |
| 16 | * CPU Extended Control register specific definitions |
| 17 | ******************************************************************************/ |
| 18 | #define CORTEX_MAKALU_CPUECTLR_EL1 S3_0_C15_C1_4 |
| 19 | |
| 20 | /******************************************************************************* |
| 21 | * CPU Power Control register specific definitions |
| 22 | ******************************************************************************/ |
| 23 | #define CORTEX_MAKALU_CPUPWRCTLR_EL1 S3_0_C15_C2_7 |
| 24 | #define CORTEX_MAKALU_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) |
| 25 | |
| 26 | #endif /* CORTEX_MAKALU_H */ |