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Nariman Poushin0ece80f2018-02-26 06:52:04 +00001/*
2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <plat_arm.h>
Nariman Poushin0ece80f2018-02-26 06:52:04 +00008
9/* Topology */
10/*
11 * The power domain tree descriptor. The cluster power domains are
12 * arranged so that when the PSCI generic code creates the power domain tree,
13 * the indices of the CPU power domain nodes it allocates match the linear
14 * indices returned by plat_core_pos_by_mpidr().
15 */
16const unsigned char sgi_pd_tree_desc[] = {
17 PLAT_ARM_CLUSTER_COUNT,
Vishwanatha HG64f0b6f2018-05-08 17:15:37 +053018 CSS_SGI_MAX_CPUS_PER_CLUSTER,
19 CSS_SGI_MAX_CPUS_PER_CLUSTER
Nariman Poushin0ece80f2018-02-26 06:52:04 +000020};
21
Nariman Poushin0ece80f2018-02-26 06:52:04 +000022/*******************************************************************************
23 * This function returns the topology tree information.
24 ******************************************************************************/
25const unsigned char *plat_get_power_domain_tree_desc(void)
26{
Chandni Cherukuria5d44ec2018-08-14 15:25:34 +053027 return sgi_pd_tree_desc;
Nariman Poushin0ece80f2018-02-26 06:52:04 +000028}
29
30/*******************************************************************************
31 * This function returns the core count within the cluster corresponding to
32 * `mpidr`.
33 ******************************************************************************/
34unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr)
35{
Chandni Cherukuria5d44ec2018-08-14 15:25:34 +053036 return CSS_SGI_MAX_CPUS_PER_CLUSTER;
Nariman Poushin0ece80f2018-02-26 06:52:04 +000037}
Chandni Cherukurid61a7052018-08-01 15:58:48 +053038
39/*******************************************************************************
40 * The array mapping platform core position (implemented by plat_my_core_pos())
41 * to the SCMI power domain ID implemented by SCP.
42 ******************************************************************************/
43const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[32] = {
44 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
45 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31
46};
Chandni Cherukuri449db452018-08-16 13:45:17 +053047
48/******************************************************************************
49 * Return the number of PE's supported by the CPU.
50 *****************************************************************************/
51unsigned int plat_arm_get_cpu_pe_count(u_register_t mpidr)
52{
53 return CSS_SGI_MAX_PE_PER_CPU;
54}