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Muhammad Hadi Asyrafi Abdul Halimc0d4d932019-03-19 17:59:06 +08001/*
Jit Loon Lim50806062023-05-17 12:26:11 +08002 * Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
Muhammad Hadi Asyrafi Abdul Halimc0d4d932019-03-19 17:59:06 +08003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Hadi Asyrafic461add2019-06-12 11:24:12 +08007#ifndef CAD_WATCHDOG_H
8#define CAD_WATCHDOG_H
Muhammad Hadi Asyrafi Abdul Halimc0d4d932019-03-19 17:59:06 +08009
Jit Loon Lim50806062023-05-17 12:26:11 +080010#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
11#define WDT_BASE (0x10D00200)
12#else
Muhammad Hadi Asyrafi Abdul Halimc0d4d932019-03-19 17:59:06 +080013#define WDT_BASE (0xFFD00200)
Jit Loon Lim50806062023-05-17 12:26:11 +080014#endif
Muhammad Hadi Asyrafi Abdul Halimc0d4d932019-03-19 17:59:06 +080015#define WDT_REG_SIZE_OFFSET (0x4)
16#define WDT_MIN_CYCLES (65536)
17#define WDT_PERIOD (20)
18
19#define WDT_CR (WDT_BASE + 0x0)
20#define WDT_TORR (WDT_BASE + 0x4)
21
22#define WDT_CRR (WDT_BASE + 0xC)
23
24#define WDT_CCVR (WDT_BASE + 0x8)
25#define WDT_STAT (WDT_BASE + 0x10)
26#define WDT_EOI (WDT_BASE + 0x14)
27
28#define WDT_COMP_PARAM_1 (WDT_BASE + 0xF4)
29#define WDT_COMP_VERSION (WDT_BASE + 0xF8)
30#define WDT_COMP_TYPE (WDT_BASE + 0XFC)
31
32#define WDT_CR_RMOD (0x0)
33#define WDT_CR_EN (0x1)
34
35#define WDT_SW_RST (0x76)
36
37
38void watchdog_init(int watchdog_clk);
Muhammad Hadi Asyrafi Abdul Halimc0d4d932019-03-19 17:59:06 +080039void watchdog_info(void);
40void watchdog_status(void);
41void watchdog_sw_rst(void);
42
43#endif