Soby Mathew | 12012dd | 2015-10-26 14:01:53 +0000 | [diff] [blame] | 1 | /* |
Madhukar Pappireddy | dc4b8c6 | 2023-08-03 12:13:27 -0500 | [diff] [blame] | 2 | * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved. |
Florian Lugou | d4e2503 | 2021-09-08 12:40:24 +0200 | [diff] [blame] | 3 | * Portions copyright (c) 2021-2022, ProvenRun S.A.S. All rights reserved. |
Soby Mathew | 12012dd | 2015-10-26 14:01:53 +0000 | [diff] [blame] | 4 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 5 | * SPDX-License-Identifier: BSD-3-Clause |
Soby Mathew | 12012dd | 2015-10-26 14:01:53 +0000 | [diff] [blame] | 6 | */ |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 7 | |
Soby Mathew | 12012dd | 2015-10-26 14:01:53 +0000 | [diff] [blame] | 8 | #include <assert.h> |
Antonio Nino Diaz | a4210cb | 2018-08-21 09:44:43 +0100 | [diff] [blame] | 9 | #include <stdbool.h> |
Soby Mathew | 12012dd | 2015-10-26 14:01:53 +0000 | [diff] [blame] | 10 | |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 11 | #include <bl31/interrupt_mgmt.h> |
| 12 | #include <drivers/arm/gic_common.h> |
| 13 | #include <drivers/arm/gicv2.h> |
| 14 | #include <plat/common/platform.h> |
| 15 | |
Soby Mathew | 12012dd | 2015-10-26 14:01:53 +0000 | [diff] [blame] | 16 | /* |
| 17 | * The following platform GIC functions are weakly defined. They |
| 18 | * provide typical implementations that may be re-used by multiple |
| 19 | * platforms but may also be overridden by a platform if required. |
| 20 | */ |
| 21 | #pragma weak plat_ic_get_pending_interrupt_id |
| 22 | #pragma weak plat_ic_get_pending_interrupt_type |
| 23 | #pragma weak plat_ic_acknowledge_interrupt |
| 24 | #pragma weak plat_ic_get_interrupt_type |
| 25 | #pragma weak plat_ic_end_of_interrupt |
| 26 | #pragma weak plat_interrupt_type_to_line |
| 27 | |
Jeenu Viswambharan | b1e957e | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 28 | #pragma weak plat_ic_get_running_priority |
Jeenu Viswambharan | 522a465 | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 29 | #pragma weak plat_ic_is_spi |
| 30 | #pragma weak plat_ic_is_ppi |
| 31 | #pragma weak plat_ic_is_sgi |
Jeenu Viswambharan | 24e7029 | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 32 | #pragma weak plat_ic_get_interrupt_active |
Jeenu Viswambharan | 0fcdfff | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 33 | #pragma weak plat_ic_enable_interrupt |
| 34 | #pragma weak plat_ic_disable_interrupt |
Jeenu Viswambharan | 447b89d | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 35 | #pragma weak plat_ic_set_interrupt_priority |
Jeenu Viswambharan | c06f05c | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 36 | #pragma weak plat_ic_set_interrupt_type |
Jeenu Viswambharan | ab14e9b | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 37 | #pragma weak plat_ic_raise_el3_sgi |
Florian Lugou | d4e2503 | 2021-09-08 12:40:24 +0200 | [diff] [blame] | 38 | #pragma weak plat_ic_raise_ns_sgi |
| 39 | #pragma weak plat_ic_raise_s_el1_sgi |
Jeenu Viswambharan | dce70b3 | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 40 | #pragma weak plat_ic_set_spi_routing |
Jeenu Viswambharan | b1e957e | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 41 | |
Soby Mathew | 12012dd | 2015-10-26 14:01:53 +0000 | [diff] [blame] | 42 | /* |
| 43 | * This function returns the highest priority pending interrupt at |
| 44 | * the Interrupt controller |
| 45 | */ |
| 46 | uint32_t plat_ic_get_pending_interrupt_id(void) |
| 47 | { |
| 48 | unsigned int id; |
| 49 | |
| 50 | id = gicv2_get_pending_interrupt_id(); |
| 51 | if (id == GIC_SPURIOUS_INTERRUPT) |
| 52 | return INTR_ID_UNAVAILABLE; |
| 53 | |
| 54 | return id; |
| 55 | } |
| 56 | |
| 57 | /* |
| 58 | * This function returns the type of the highest priority pending interrupt |
| 59 | * at the Interrupt controller. In the case of GICv2, the Highest Priority |
| 60 | * Pending interrupt register (`GICC_HPPIR`) is read to determine the id of |
| 61 | * the pending interrupt. The type of interrupt depends upon the id value |
| 62 | * as follows. |
| 63 | * 1. id < PENDING_G1_INTID (1022) is reported as a S-EL1 interrupt |
| 64 | * 2. id = PENDING_G1_INTID (1022) is reported as a Non-secure interrupt. |
| 65 | * 3. id = GIC_SPURIOUS_INTERRUPT (1023) is reported as an invalid interrupt |
| 66 | * type. |
| 67 | */ |
| 68 | uint32_t plat_ic_get_pending_interrupt_type(void) |
| 69 | { |
| 70 | unsigned int id; |
| 71 | |
| 72 | id = gicv2_get_pending_interrupt_type(); |
| 73 | |
| 74 | /* Assume that all secure interrupts are S-EL1 interrupts */ |
Jeenu Viswambharan | c06f05c | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 75 | if (id < PENDING_G1_INTID) { |
| 76 | #if GICV2_G0_FOR_EL3 |
| 77 | return INTR_TYPE_EL3; |
| 78 | #else |
Soby Mathew | 12012dd | 2015-10-26 14:01:53 +0000 | [diff] [blame] | 79 | return INTR_TYPE_S_EL1; |
Jeenu Viswambharan | c06f05c | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 80 | #endif |
| 81 | } |
Soby Mathew | 12012dd | 2015-10-26 14:01:53 +0000 | [diff] [blame] | 82 | |
| 83 | if (id == GIC_SPURIOUS_INTERRUPT) |
| 84 | return INTR_TYPE_INVAL; |
| 85 | |
| 86 | return INTR_TYPE_NS; |
| 87 | } |
| 88 | |
| 89 | /* |
| 90 | * This function returns the highest priority pending interrupt at |
| 91 | * the Interrupt controller and indicates to the Interrupt controller |
| 92 | * that the interrupt processing has started. |
| 93 | */ |
| 94 | uint32_t plat_ic_acknowledge_interrupt(void) |
| 95 | { |
| 96 | return gicv2_acknowledge_interrupt(); |
| 97 | } |
| 98 | |
| 99 | /* |
| 100 | * This function returns the type of the interrupt `id`, depending on how |
| 101 | * the interrupt has been configured in the interrupt controller |
| 102 | */ |
| 103 | uint32_t plat_ic_get_interrupt_type(uint32_t id) |
| 104 | { |
| 105 | unsigned int type; |
| 106 | |
| 107 | type = gicv2_get_interrupt_group(id); |
| 108 | |
| 109 | /* Assume that all secure interrupts are S-EL1 interrupts */ |
Antonio Nino Diaz | a4210cb | 2018-08-21 09:44:43 +0100 | [diff] [blame] | 110 | return (type == GICV2_INTR_GROUP1) ? INTR_TYPE_NS : |
Jeenu Viswambharan | c06f05c | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 111 | #if GICV2_G0_FOR_EL3 |
| 112 | INTR_TYPE_EL3; |
| 113 | #else |
| 114 | INTR_TYPE_S_EL1; |
| 115 | #endif |
Soby Mathew | 12012dd | 2015-10-26 14:01:53 +0000 | [diff] [blame] | 116 | } |
| 117 | |
| 118 | /* |
| 119 | * This functions is used to indicate to the interrupt controller that |
| 120 | * the processing of the interrupt corresponding to the `id` has |
| 121 | * finished. |
| 122 | */ |
| 123 | void plat_ic_end_of_interrupt(uint32_t id) |
| 124 | { |
| 125 | gicv2_end_of_interrupt(id); |
| 126 | } |
| 127 | |
| 128 | /* |
| 129 | * An ARM processor signals interrupt exceptions through the IRQ and FIQ pins. |
| 130 | * The interrupt controller knows which pin/line it uses to signal a type of |
| 131 | * interrupt. It lets the interrupt management framework determine |
| 132 | * for a type of interrupt and security state, which line should be used in the |
| 133 | * SCR_EL3 to control its routing to EL3. The interrupt line is represented |
| 134 | * as the bit position of the IRQ or FIQ bit in the SCR_EL3. |
| 135 | */ |
| 136 | uint32_t plat_interrupt_type_to_line(uint32_t type, |
| 137 | uint32_t security_state) |
| 138 | { |
Antonio Nino Diaz | a4210cb | 2018-08-21 09:44:43 +0100 | [diff] [blame] | 139 | assert((type == INTR_TYPE_S_EL1) || (type == INTR_TYPE_EL3) || |
| 140 | (type == INTR_TYPE_NS)); |
Soby Mathew | 12012dd | 2015-10-26 14:01:53 +0000 | [diff] [blame] | 141 | |
Santeri Salko | 4ed2338 | 2018-02-08 22:01:26 +0200 | [diff] [blame] | 142 | assert(sec_state_is_valid(security_state)); |
| 143 | |
Soby Mathew | 12012dd | 2015-10-26 14:01:53 +0000 | [diff] [blame] | 144 | /* Non-secure interrupts are signaled on the IRQ line always */ |
| 145 | if (type == INTR_TYPE_NS) |
| 146 | return __builtin_ctz(SCR_IRQ_BIT); |
| 147 | |
| 148 | /* |
| 149 | * Secure interrupts are signaled using the IRQ line if the FIQ is |
| 150 | * not enabled else they are signaled using the FIQ line. |
| 151 | */ |
Antonio Nino Diaz | a4210cb | 2018-08-21 09:44:43 +0100 | [diff] [blame] | 152 | return ((gicv2_is_fiq_enabled() != 0U) ? __builtin_ctz(SCR_FIQ_BIT) : |
| 153 | __builtin_ctz(SCR_IRQ_BIT)); |
Soby Mathew | 12012dd | 2015-10-26 14:01:53 +0000 | [diff] [blame] | 154 | } |
Jeenu Viswambharan | b1e957e | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 155 | |
| 156 | unsigned int plat_ic_get_running_priority(void) |
| 157 | { |
| 158 | return gicv2_get_running_priority(); |
| 159 | } |
Jeenu Viswambharan | 522a465 | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 160 | |
| 161 | int plat_ic_is_spi(unsigned int id) |
| 162 | { |
| 163 | return (id >= MIN_SPI_ID) && (id <= MAX_SPI_ID); |
| 164 | } |
| 165 | |
| 166 | int plat_ic_is_ppi(unsigned int id) |
| 167 | { |
| 168 | return (id >= MIN_PPI_ID) && (id < MIN_SPI_ID); |
| 169 | } |
| 170 | |
| 171 | int plat_ic_is_sgi(unsigned int id) |
| 172 | { |
| 173 | return (id >= MIN_SGI_ID) && (id < MIN_PPI_ID); |
| 174 | } |
Jeenu Viswambharan | 24e7029 | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 175 | |
| 176 | unsigned int plat_ic_get_interrupt_active(unsigned int id) |
| 177 | { |
| 178 | return gicv2_get_interrupt_active(id); |
| 179 | } |
Jeenu Viswambharan | 0fcdfff | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 180 | |
| 181 | void plat_ic_enable_interrupt(unsigned int id) |
| 182 | { |
| 183 | gicv2_enable_interrupt(id); |
| 184 | } |
| 185 | |
| 186 | void plat_ic_disable_interrupt(unsigned int id) |
| 187 | { |
| 188 | gicv2_disable_interrupt(id); |
| 189 | } |
Jeenu Viswambharan | 447b89d | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 190 | |
| 191 | void plat_ic_set_interrupt_priority(unsigned int id, unsigned int priority) |
| 192 | { |
| 193 | gicv2_set_interrupt_priority(id, priority); |
| 194 | } |
Jeenu Viswambharan | c06f05c | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 195 | |
| 196 | int plat_ic_has_interrupt_type(unsigned int type) |
| 197 | { |
Jonathan Wright | ff957ed | 2018-03-14 15:24:00 +0000 | [diff] [blame] | 198 | int has_interrupt_type = 0; |
| 199 | |
Jeenu Viswambharan | c06f05c | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 200 | switch (type) { |
| 201 | #if GICV2_G0_FOR_EL3 |
| 202 | case INTR_TYPE_EL3: |
| 203 | #else |
| 204 | case INTR_TYPE_S_EL1: |
| 205 | #endif |
| 206 | case INTR_TYPE_NS: |
Jonathan Wright | ff957ed | 2018-03-14 15:24:00 +0000 | [diff] [blame] | 207 | has_interrupt_type = 1; |
| 208 | break; |
Jeenu Viswambharan | c06f05c | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 209 | default: |
Jonathan Wright | ff957ed | 2018-03-14 15:24:00 +0000 | [diff] [blame] | 210 | /* Do nothing in default case */ |
| 211 | break; |
Jeenu Viswambharan | c06f05c | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 212 | } |
Jonathan Wright | ff957ed | 2018-03-14 15:24:00 +0000 | [diff] [blame] | 213 | |
| 214 | return has_interrupt_type; |
Jeenu Viswambharan | c06f05c | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 215 | } |
| 216 | |
| 217 | void plat_ic_set_interrupt_type(unsigned int id, unsigned int type) |
| 218 | { |
Madhukar Pappireddy | dc4b8c6 | 2023-08-03 12:13:27 -0500 | [diff] [blame] | 219 | unsigned int gicv2_group = 0U; |
Jeenu Viswambharan | c06f05c | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 220 | |
| 221 | /* Map canonical interrupt type to GICv2 type */ |
| 222 | switch (type) { |
| 223 | #if GICV2_G0_FOR_EL3 |
| 224 | case INTR_TYPE_EL3: |
| 225 | #else |
| 226 | case INTR_TYPE_S_EL1: |
| 227 | #endif |
Madhukar Pappireddy | dc4b8c6 | 2023-08-03 12:13:27 -0500 | [diff] [blame] | 228 | gicv2_group = GICV2_INTR_GROUP0; |
Jeenu Viswambharan | c06f05c | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 229 | break; |
| 230 | case INTR_TYPE_NS: |
Madhukar Pappireddy | dc4b8c6 | 2023-08-03 12:13:27 -0500 | [diff] [blame] | 231 | gicv2_group = GICV2_INTR_GROUP1; |
Jeenu Viswambharan | c06f05c | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 232 | break; |
| 233 | default: |
Madhukar Pappireddy | dc4b8c6 | 2023-08-03 12:13:27 -0500 | [diff] [blame] | 234 | assert(false); /* Unreachable */ |
Jonathan Wright | ff957ed | 2018-03-14 15:24:00 +0000 | [diff] [blame] | 235 | break; |
Jeenu Viswambharan | c06f05c | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 236 | } |
| 237 | |
Madhukar Pappireddy | dc4b8c6 | 2023-08-03 12:13:27 -0500 | [diff] [blame] | 238 | gicv2_set_interrupt_group(id, gicv2_group); |
Jeenu Viswambharan | c06f05c | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 239 | } |
Jeenu Viswambharan | ab14e9b | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 240 | |
| 241 | void plat_ic_raise_el3_sgi(int sgi_num, u_register_t target) |
| 242 | { |
| 243 | #if GICV2_G0_FOR_EL3 |
| 244 | int id; |
| 245 | |
| 246 | /* Target must be a valid MPIDR in the system */ |
| 247 | id = plat_core_pos_by_mpidr(target); |
| 248 | assert(id >= 0); |
| 249 | |
| 250 | /* Verify that this is a secure SGI */ |
| 251 | assert(plat_ic_get_interrupt_type(sgi_num) == INTR_TYPE_EL3); |
| 252 | |
Florian Lugou | d4e2503 | 2021-09-08 12:40:24 +0200 | [diff] [blame] | 253 | gicv2_raise_sgi(sgi_num, false, id); |
Jeenu Viswambharan | ab14e9b | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 254 | #else |
Antonio Nino Diaz | a4210cb | 2018-08-21 09:44:43 +0100 | [diff] [blame] | 255 | assert(false); |
Jeenu Viswambharan | ab14e9b | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 256 | #endif |
| 257 | } |
Jeenu Viswambharan | dce70b3 | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 258 | |
Florian Lugou | d4e2503 | 2021-09-08 12:40:24 +0200 | [diff] [blame] | 259 | void plat_ic_raise_ns_sgi(int sgi_num, u_register_t target) |
| 260 | { |
| 261 | int id; |
| 262 | |
| 263 | /* Target must be a valid MPIDR in the system */ |
| 264 | id = plat_core_pos_by_mpidr(target); |
| 265 | assert(id >= 0); |
| 266 | |
| 267 | /* Verify that this is a non-secure SGI */ |
| 268 | assert(plat_ic_get_interrupt_type(sgi_num) == INTR_TYPE_NS); |
| 269 | |
| 270 | gicv2_raise_sgi(sgi_num, true, id); |
| 271 | } |
| 272 | |
| 273 | void plat_ic_raise_s_el1_sgi(int sgi_num, u_register_t target) |
| 274 | { |
| 275 | #if GICV2_G0_FOR_EL3 |
| 276 | assert(false); |
| 277 | #else |
| 278 | int id; |
| 279 | |
| 280 | /* Target must be a valid MPIDR in the system */ |
| 281 | id = plat_core_pos_by_mpidr(target); |
| 282 | assert(id >= 0); |
| 283 | |
| 284 | /* Verify that this is a secure EL1 SGI */ |
| 285 | assert(plat_ic_get_interrupt_type(sgi_num) == INTR_TYPE_S_EL1); |
| 286 | |
| 287 | gicv2_raise_sgi(sgi_num, false, id); |
| 288 | #endif |
| 289 | } |
| 290 | |
Jeenu Viswambharan | dce70b3 | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 291 | void plat_ic_set_spi_routing(unsigned int id, unsigned int routing_mode, |
| 292 | u_register_t mpidr) |
| 293 | { |
| 294 | int proc_num = 0; |
| 295 | |
| 296 | switch (routing_mode) { |
| 297 | case INTR_ROUTING_MODE_PE: |
| 298 | proc_num = plat_core_pos_by_mpidr(mpidr); |
| 299 | assert(proc_num >= 0); |
| 300 | break; |
| 301 | case INTR_ROUTING_MODE_ANY: |
| 302 | /* Bit mask selecting all 8 CPUs as candidates */ |
| 303 | proc_num = -1; |
| 304 | break; |
| 305 | default: |
Daniel Boulby | 8942a1b | 2018-06-22 14:16:03 +0100 | [diff] [blame] | 306 | assert(0); /* Unreachable */ |
Jonathan Wright | ff957ed | 2018-03-14 15:24:00 +0000 | [diff] [blame] | 307 | break; |
Jeenu Viswambharan | dce70b3 | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 308 | } |
| 309 | |
| 310 | gicv2_set_spi_routing(id, proc_num); |
| 311 | } |
Jeenu Viswambharan | eb1c12c | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 312 | |
| 313 | void plat_ic_set_interrupt_pending(unsigned int id) |
| 314 | { |
| 315 | gicv2_set_interrupt_pending(id); |
| 316 | } |
| 317 | |
| 318 | void plat_ic_clear_interrupt_pending(unsigned int id) |
| 319 | { |
| 320 | gicv2_clear_interrupt_pending(id); |
| 321 | } |
Jeenu Viswambharan | 6250507 | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 322 | |
| 323 | unsigned int plat_ic_set_priority_mask(unsigned int mask) |
| 324 | { |
| 325 | return gicv2_set_pmr(mask); |
| 326 | } |
Jeenu Viswambharan | 055af4b | 2017-10-24 15:13:59 +0100 | [diff] [blame] | 327 | |
| 328 | unsigned int plat_ic_get_interrupt_id(unsigned int raw) |
| 329 | { |
| 330 | unsigned int id = (raw & INT_ID_MASK); |
| 331 | |
| 332 | if (id == GIC_SPURIOUS_INTERRUPT) |
| 333 | id = INTR_ID_UNAVAILABLE; |
| 334 | |
| 335 | return id; |
| 336 | } |