| Paul Beesley | 9774302 | 2019-07-12 11:37:07 +0100 | [diff] [blame] | 1 | Marvell IO WIN address decoding bindings |
| 2 | ======================================== |
| 3 | |
| 4 | IO Window configration driver (2nd stage address translation) for Marvell Armada 8K and 8K+ SoCs. |
| 5 | |
| 6 | The IO WIN includes a description of the address decoding configuration. |
| 7 | |
| 8 | Transactions that are decoded by CCU windows as IO peripheral, have an additional |
| 9 | layer of decoding. This additional address decoding layer defines one of the |
| 10 | following targets: |
| 11 | |
| 12 | - **0x0** = BootRom |
| 13 | - **0x1** = STM (Serial Trace Macro-cell, a programmer's port into trace stream) |
| 14 | - **0x2** = SPI direct access |
| 15 | - **0x3** = PCIe registers |
| 16 | - **0x4** = MCI Port |
| 17 | - **0x5** = PCIe port |
| 18 | |
| 19 | Mandatory functions |
| 20 | ------------------- |
| 21 | |
| 22 | - marvell_get_io_win_memory_map |
| 23 | Returns the IO windows configuration and the number of windows of the |
| 24 | specific AP. |
| 25 | |
| 26 | Mandatory structures |
| 27 | -------------------- |
| 28 | |
| 29 | - io_win_memory_map |
| 30 | Array that include the configuration of the windows. Every window/entry is |
| 31 | a struct which has 3 parameters: |
| 32 | |
| 33 | - Base address of the window |
| 34 | - Size of the window |
| 35 | - Target-ID of the window |
| 36 | |
| 37 | Example |
| 38 | ------- |
| 39 | |
| 40 | .. code:: c |
| 41 | |
| 42 | struct addr_map_win io_win_memory_map[] = { |
| 43 | {0x00000000fe000000, 0x000000001f00000, PCIE_PORT_TID}, /* PCIe window 31Mb for PCIe port*/ |
| 44 | {0x00000000ffe00000, 0x000000000100000, PCIE_REGS_TID}, /* PCI-REG window 64Kb for PCIe-reg*/ |
| 45 | {0x00000000f6000000, 0x000000000100000, MCIPHY_TID}, /* MCI window 1Mb for PHY-reg*/ |
| 46 | }; |