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git01.mediatek.com / filogic / atf / 8181f28047c4f369067a24da75cefa9f8a0651d0 / . / fdts / stm32mp131.dtsi
blob: 2c62408515b776250bcea0b4726c6a002a2087fb [file] [log] [blame]
Yann Gautiercd736192020-02-25 15:14:52 +0100[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (C) STMicroelectronics 2022 - All Rights Reserved
4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
5 */
6#include <dt-bindings/clock/stm32mp13-clks.h>
7#include <dt-bindings/interrupt-controller/arm-gic.h>
8#include <dt-bindings/reset/stm32mp13-resets.h>
9
10/ {
11 #address-cells = <1>;
12 #size-cells = <1>;
13
14 cpus {
15 #address-cells = <1>;
16 #size-cells = <0>;
17
18 cpu0: cpu@0 {
19 compatible = "arm,cortex-a7";
20 device_type = "cpu";
21 reg = <0>;
22 clocks = <&rcc CK_MPU>;
23 clock-names = "cpu";
24 nvmem-cells = <&part_number_otp>;
25 nvmem-cell-names = "part_number";
26 };
27 };
28
Yann Gautiercd736192020-02-25 15:14:52 +0100[diff] [blame]29 clocks {
30 clk_csi: clk-csi {
31 #clock-cells = <0>;
32 compatible = "fixed-clock";
33 clock-frequency = <4000000>;
34 };
35
36 clk_hse: clk-hse {
37 #clock-cells = <0>;
38 compatible = "fixed-clock";
39 clock-frequency = <24000000>;
40 };
41
42 clk_hsi: clk-hsi {
43 #clock-cells = <0>;
44 compatible = "fixed-clock";
45 clock-frequency = <64000000>;
46 };
47
48 clk_lse: clk-lse {
49 #clock-cells = <0>;
50 compatible = "fixed-clock";
51 clock-frequency = <32768>;
52 };
53
54 clk_lsi: clk-lsi {
55 #clock-cells = <0>;
56 compatible = "fixed-clock";
57 clock-frequency = <32000>;
58 };
59 };
60
61 intc: interrupt-controller@a0021000 {
62 compatible = "arm,cortex-a7-gic";
63 #interrupt-cells = <3>;
64 interrupt-controller;
65 reg = <0xa0021000 0x1000>,
66 <0xa0022000 0x2000>;
67 };
68
69 psci {
70 compatible = "arm,psci-1.0";
71 method = "smc";
72 };
73
74 soc {
75 compatible = "simple-bus";
76 #address-cells = <1>;
77 #size-cells = <1>;
78 interrupt-parent = <&intc>;
79 ranges;
80
81 usart3: serial@4000f000 {
82 compatible = "st,stm32h7-uart";
83 reg = <0x4000f000 0x400>;
84 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
85 clocks = <&rcc USART3_K>;
86 resets = <&rcc USART3_R>;
87 status = "disabled";
88 };
89
90 uart4: serial@40010000 {
91 compatible = "st,stm32h7-uart";
92 reg = <0x40010000 0x400>;
93 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
94 clocks = <&rcc UART4_K>;
95 resets = <&rcc UART4_R>;
96 status = "disabled";
97 };
98
99 uart5: serial@40011000 {
100 compatible = "st,stm32h7-uart";
101 reg = <0x40011000 0x400>;
102 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
103 clocks = <&rcc UART5_K>;
104 resets = <&rcc UART5_R>;
105 status = "disabled";
106 };
107
108 uart7: serial@40018000 {
109 compatible = "st,stm32h7-uart";
110 reg = <0x40018000 0x400>;
111 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
112 clocks = <&rcc UART7_K>;
113 resets = <&rcc UART7_R>;
114 status = "disabled";
115 };
116
117 uart8: serial@40019000 {
118 compatible = "st,stm32h7-uart";
119 reg = <0x40019000 0x400>;
120 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
121 clocks = <&rcc UART8_K>;
122 resets = <&rcc UART8_R>;
123 status = "disabled";
124 };
125
126 usart6: serial@44003000 {
127 compatible = "st,stm32h7-uart";
128 reg = <0x44003000 0x400>;
129 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
130 clocks = <&rcc USART6_K>;
131 resets = <&rcc USART6_R>;
132 status = "disabled";
133 };
134
135 usbotg_hs: usb-otg@49000000 {
136 compatible = "st,stm32mp15-hsotg", "snps,dwc2";
137 reg = <0x49000000 0x40000>;
138 clocks = <&rcc USBO_K>;
139 clock-names = "otg";
140 resets = <&rcc USBO_R>;
141 reset-names = "dwc2";
142 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
143 g-rx-fifo-size = <512>;
144 g-np-tx-fifo-size = <32>;
145 g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
146 dr_mode = "otg";
147 usb33d-supply = <&usb33>;
148 status = "disabled";
149 };
150
151 usart1: serial@4c000000 {
152 compatible = "st,stm32h7-uart";
153 reg = <0x4c000000 0x400>;
154 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
155 clocks = <&rcc USART1_K>;
156 resets = <&rcc USART1_R>;
157 status = "disabled";
158 };
159
160 usart2: serial@4c001000 {
161 compatible = "st,stm32h7-uart";
162 reg = <0x4c001000 0x400>;
163 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
164 clocks = <&rcc USART2_K>;
165 resets = <&rcc USART2_R>;
166 status = "disabled";
167 };
168
169 i2c3: i2c@4c004000 {
170 compatible = "st,stm32mp13-i2c";
171 reg = <0x4c004000 0x400>;
172 interrupt-names = "event", "error";
173 interrupts-extended = <&exti 23 IRQ_TYPE_LEVEL_HIGH>,
174 <&intc GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
175 clocks = <&rcc I2C3_K>;
176 resets = <&rcc I2C3_R>;
177 #address-cells = <1>;
178 #size-cells = <0>;
179 st,syscfg-fmp = <&syscfg 0x4 0x4>;
180 i2c-analog-filter;
181 status = "disabled";
182 };
183
184 i2c4: i2c@4c005000 {
185 compatible = "st,stm32mp13-i2c";
186 reg = <0x4c005000 0x400>;
187 interrupt-names = "event", "error";
188 interrupts-extended = <&exti 24 IRQ_TYPE_LEVEL_HIGH>,
189 <&intc GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
190 clocks = <&rcc I2C4_K>;
191 resets = <&rcc I2C4_R>;
192 #address-cells = <1>;
193 #size-cells = <0>;
194 st,syscfg-fmp = <&syscfg 0x4 0x8>;
195 i2c-analog-filter;
196 status = "disabled";
197 };
198
199 i2c5: i2c@4c006000 {
200 compatible = "st,stm32mp13-i2c";
201 reg = <0x4c006000 0x400>;
202 interrupt-names = "event", "error";
203 interrupts-extended = <&exti 25 IRQ_TYPE_LEVEL_HIGH>,
204 <&intc GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
205 clocks = <&rcc I2C5_K>;
206 resets = <&rcc I2C5_R>;
207 #address-cells = <1>;
208 #size-cells = <0>;
209 st,syscfg-fmp = <&syscfg 0x4 0x10>;
210 i2c-analog-filter;
211 status = "disabled";
212 };
213
214 rcc: rcc@50000000 {
215 compatible = "st,stm32mp13-rcc", "syscon";
216 reg = <0x50000000 0x1000>;
217 #address-cells = <1>;
218 #size-cells = <0>;
219 #clock-cells = <1>;
220 #reset-cells = <1>;
221 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
222 secure-interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
223 secure-interrupt-names = "wakeup";
224 };
225
226 pwr_regulators: pwr@50001000 {
227 compatible = "st,stm32mp1,pwr-reg";
228 reg = <0x50001000 0x10>;
229
230 reg11: reg11 {
231 regulator-name = "reg11";
232 regulator-min-microvolt = <1100000>;
233 regulator-max-microvolt = <1100000>;
234 };
235
236 reg18: reg18 {
237 regulator-name = "reg18";
238 regulator-min-microvolt = <1800000>;
239 regulator-max-microvolt = <1800000>;
240 };
241
242 usb33: usb33 {
243 regulator-name = "usb33";
244 regulator-min-microvolt = <3300000>;
245 regulator-max-microvolt = <3300000>;
246 };
247 };
248
249 exti: interrupt-controller@5000d000 {
250 compatible = "st,stm32mp13-exti", "syscon";
251 interrupt-controller;
252 #interrupt-cells = <2>;
253 reg = <0x5000d000 0x400>;
254 };
255
256 syscfg: syscon@50020000 {
257 compatible = "st,stm32mp157-syscfg", "syscon";
258 reg = <0x50020000 0x400>;
259 clocks = <&rcc SYSCFG>;
260 };
261
Yann Gautiercd736192020-02-25 15:14:52 +0100[diff] [blame]262 hash: hash@54003000 {
263 compatible = "st,stm32mp13-hash";
264 reg = <0x54003000 0x400>;
265 clocks = <&rcc HASH1>;
266 resets = <&rcc HASH1_R>;
267 status = "disabled";
268 };
269
270 rng: rng@54004000 {
271 compatible = "st,stm32mp13-rng";
272 reg = <0x54004000 0x400>;
273 clocks = <&rcc RNG1_K>;
274 resets = <&rcc RNG1_R>;
275 status = "disabled";
276 };
277
278 fmc: memory-controller@58002000 {
279 #address-cells = <2>;
280 #size-cells = <1>;
281 compatible = "st,stm32mp1-fmc2-ebi";
282 reg = <0x58002000 0x1000>;
283 clocks = <&rcc FMC_K>;
284 resets = <&rcc FMC_R>;
285 status = "disabled";
286
287 ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
288 <1 0 0x64000000 0x04000000>, /* EBI CS 2 */
289 <2 0 0x68000000 0x04000000>, /* EBI CS 3 */
290 <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
291 <4 0 0x80000000 0x10000000>; /* NAND */
292
293 nand-controller@4,0 {
294 #address-cells = <1>;
295 #size-cells = <0>;
296 compatible = "st,stm32mp1-fmc2-nfc";
297 reg = <4 0x00000000 0x1000>,
298 <4 0x08010000 0x1000>,
299 <4 0x08020000 0x1000>,
300 <4 0x01000000 0x1000>,
301 <4 0x09010000 0x1000>,
302 <4 0x09020000 0x1000>;
303 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
304 status = "disabled";
305 };
306 };
307
308 qspi: spi@58003000 {
309 compatible = "st,stm32f469-qspi";
310 reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
311 reg-names = "qspi", "qspi_mm";
312 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
313 clocks = <&rcc QSPI_K>;
314 resets = <&rcc QSPI_R>;
315 status = "disabled";
316 };
317
318 sdmmc1: mmc@58005000 {
319 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
320 arm,primecell-periphid = <0x20253180>;
321 reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
322 clocks = <&rcc SDMMC1_K>;
323 clock-names = "apb_pclk";
324 resets = <&rcc SDMMC1_R>;
325 cap-sd-highspeed;
326 cap-mmc-highspeed;
Yann Gautierb2f654f2022-05-02 13:54:21 +0200[diff] [blame]327 max-frequency = <130000000>;
Yann Gautiercd736192020-02-25 15:14:52 +0100[diff] [blame]328 status = "disabled";
329 };
330
331 sdmmc2: mmc@58007000 {
332 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
333 arm,primecell-periphid = <0x20253180>;
334 reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
335 clocks = <&rcc SDMMC2_K>;
336 clock-names = "apb_pclk";
337 resets = <&rcc SDMMC2_R>;
338 cap-sd-highspeed;
339 cap-mmc-highspeed;
Yann Gautierb2f654f2022-05-02 13:54:21 +0200[diff] [blame]340 max-frequency = <130000000>;
Yann Gautiercd736192020-02-25 15:14:52 +0100[diff] [blame]341 status = "disabled";
342 };
343
Yann Gautiercd736192020-02-25 15:14:52 +0100[diff] [blame]344 usbh_ohci: usbh-ohci@5800c000 {
345 compatible = "generic-ohci";
346 reg = <0x5800c000 0x1000>;
347 clocks = <&rcc USBH>;
348 resets = <&rcc USBH_R>;
349 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
350 status = "disabled";
351 };
352
353 usbh_ehci: usbh-ehci@5800d000 {
354 compatible = "generic-ehci";
355 reg = <0x5800d000 0x1000>;
356 clocks = <&rcc USBH>;
357 resets = <&rcc USBH_R>;
358 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
359 companion = <&usbh_ohci>;
360 status = "disabled";
361 };
362
363 iwdg2: watchdog@5a002000 {
364 compatible = "st,stm32mp1-iwdg";
365 reg = <0x5a002000 0x400>;
366 clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
367 clock-names = "pclk", "lsi";
368 status = "disabled";
369 };
370
Johann Neuhausera5ef16a2022-07-08 15:22:05 +0200[diff] [blame]371 ddr: ddr@5a003000 {
Nicolas Le Bayon01087912021-01-12 18:18:27 +0100[diff] [blame]372 compatible = "st,stm32mp13-ddr";
373 reg = <0x5a003000 0x550>, <0x5a004000 0x234>;
374 clocks = <&rcc AXIDCG>,
375 <&rcc DDRC1>,
376 <&rcc DDRPHYC>,
377 <&rcc DDRCAPB>,
378 <&rcc DDRPHYCAPB>;
379 clock-names = "axidcg",
380 "ddrc1",
381 "ddrphyc",
382 "ddrcapb",
383 "ddrphycapb";
384 };
385
Yann Gautiercd736192020-02-25 15:14:52 +0100[diff] [blame]386 usbphyc: usbphyc@5a006000 {
387 #address-cells = <1>;
388 #size-cells = <0>;
389 #clock-cells = <0>;
390 compatible = "st,stm32mp1-usbphyc";
391 reg = <0x5a006000 0x1000>;
392 clocks = <&rcc USBPHY_K>;
393 resets = <&rcc USBPHY_R>;
394 vdda1v1-supply = <&reg11>;
395 vdda1v8-supply = <&reg18>;
396 status = "disabled";
397
398 usbphyc_port0: usb-phy@0 {
399 #phy-cells = <0>;
400 reg = <0>;
401 };
402
403 usbphyc_port1: usb-phy@1 {
404 #phy-cells = <1>;
405 reg = <1>;
406 };
407 };
408
409 iwdg1: watchdog@5c003000 {
410 compatible = "st,stm32mp1-iwdg";
411 reg = <0x5c003000 0x400>;
412 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
413 clocks = <&rcc IWDG1>, <&rcc CK_LSI>;
414 clock-names = "pclk", "lsi";
415 status = "disabled";
416 };
417
418 bsec: efuse@5c005000 {
419 compatible = "st,stm32mp15-bsec";
420 reg = <0x5c005000 0x400>;
421 #address-cells = <1>;
422 #size-cells = <1>;
423
424 cfg0_otp: cfg0_otp@0 {
425 reg = <0x0 0x2>;
426 };
427 part_number_otp: part_number_otp@4 {
428 reg = <0x4 0x2>;
429 };
430 monotonic_otp: monotonic_otp@10 {
431 reg = <0x10 0x4>;
432 };
433 nand_otp: cfg9_otp@24 {
434 reg = <0x24 0x4>;
435 };
436 nand2_otp: cfg10_otp@28 {
437 reg = <0x28 0x4>;
438 };
439 uid_otp: uid_otp@34 {
440 reg = <0x34 0xc>;
441 };
442 hw2_otp: hw2_otp@48 {
443 reg = <0x48 0x4>;
444 };
445 ts_cal1: calib@5c {
446 reg = <0x5c 0x2>;
447 };
448 ts_cal2: calib@5e {
449 reg = <0x5e 0x2>;
450 };
451 pkh_otp: pkh_otp@60 {
452 reg = <0x60 0x20>;
453 };
454 mac_addr: mac_addr@e4 {
455 reg = <0xe4 0xc>;
456 st,non-secure-otp;
457 };
458 };
Yann Gautiercd736192020-02-25 15:14:52 +0100[diff] [blame]459 /*
460 * Break node order to solve dependency probe issue between
461 * pinctrl and exti.
462 */
Yann Gautier1bbb09e2022-03-11 14:23:43 +0100[diff] [blame]463 pinctrl: pinctrl@50002000 {
Yann Gautiercd736192020-02-25 15:14:52 +0100[diff] [blame]464 #address-cells = <1>;
465 #size-cells = <1>;
466 compatible = "st,stm32mp135-pinctrl";
467 ranges = <0 0x50002000 0x8400>;
468 interrupt-parent = <&exti>;
469 st,syscfg = <&exti 0x60 0xff>;
470 pins-are-numbered;
471
472 gpioa: gpio@50002000 {
473 gpio-controller;
474 #gpio-cells = <2>;
475 interrupt-controller;
476 #interrupt-cells = <2>;
477 reg = <0x0 0x400>;
478 clocks = <&rcc GPIOA>;
479 st,bank-name = "GPIOA";
480 ngpios = <16>;
481 gpio-ranges = <&pinctrl 0 0 16>;
482 };
483
484 gpiob: gpio@50003000 {
485 gpio-controller;
486 #gpio-cells = <2>;
487 interrupt-controller;
488 #interrupt-cells = <2>;
489 reg = <0x1000 0x400>;
490 clocks = <&rcc GPIOB>;
491 st,bank-name = "GPIOB";
492 ngpios = <16>;
493 gpio-ranges = <&pinctrl 0 16 16>;
494 };
495
496 gpioc: gpio@50004000 {
497 gpio-controller;
498 #gpio-cells = <2>;
499 interrupt-controller;
500 #interrupt-cells = <2>;
501 reg = <0x2000 0x400>;
502 clocks = <&rcc GPIOC>;
503 st,bank-name = "GPIOC";
504 ngpios = <16>;
505 gpio-ranges = <&pinctrl 0 32 16>;
506 };
507
508 gpiod: gpio@50005000 {
509 gpio-controller;
510 #gpio-cells = <2>;
511 interrupt-controller;
512 #interrupt-cells = <2>;
513 reg = <0x3000 0x400>;
514 clocks = <&rcc GPIOD>;
515 st,bank-name = "GPIOD";
516 ngpios = <16>;
517 gpio-ranges = <&pinctrl 0 48 16>;
518 };
519
520 gpioe: gpio@50006000 {
521 gpio-controller;
522 #gpio-cells = <2>;
523 interrupt-controller;
524 #interrupt-cells = <2>;
525 reg = <0x4000 0x400>;
526 clocks = <&rcc GPIOE>;
527 st,bank-name = "GPIOE";
528 ngpios = <16>;
529 gpio-ranges = <&pinctrl 0 64 16>;
530 };
531
532 gpiof: gpio@50007000 {
533 gpio-controller;
534 #gpio-cells = <2>;
535 interrupt-controller;
536 #interrupt-cells = <2>;
537 reg = <0x5000 0x400>;
538 clocks = <&rcc GPIOF>;
539 st,bank-name = "GPIOF";
540 ngpios = <16>;
541 gpio-ranges = <&pinctrl 0 80 16>;
542 };
543
544 gpiog: gpio@50008000 {
545 gpio-controller;
546 #gpio-cells = <2>;
547 interrupt-controller;
548 #interrupt-cells = <2>;
549 reg = <0x6000 0x400>;
550 clocks = <&rcc GPIOG>;
551 st,bank-name = "GPIOG";
552 ngpios = <16>;
553 gpio-ranges = <&pinctrl 0 96 16>;
554 };
555
556 gpioh: gpio@50009000 {
557 gpio-controller;
558 #gpio-cells = <2>;
559 interrupt-controller;
560 #interrupt-cells = <2>;
561 reg = <0x7000 0x400>;
562 clocks = <&rcc GPIOH>;
563 st,bank-name = "GPIOH";
564 ngpios = <15>;
565 gpio-ranges = <&pinctrl 0 112 15>;
566 };
567
568 gpioi: gpio@5000a000 {
569 gpio-controller;
570 #gpio-cells = <2>;
571 interrupt-controller;
572 #interrupt-cells = <2>;
573 reg = <0x8000 0x400>;
574 clocks = <&rcc GPIOI>;
575 st,bank-name = "GPIOI";
576 ngpios = <8>;
577 gpio-ranges = <&pinctrl 0 128 8>;
578 };
579 };
580 };
581};