blob: 6998dae5700b99938cdacf3a799449c2677df7db [file] [log] [blame]
Antonio Nino Diazc41f2062017-10-24 10:07:35 +01001/*
2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <arch_helpers.h>
Antonio Nino Diazc41f2062017-10-24 10:07:35 +01009#include <assert.h>
10#include <common_def.h>
11#include <context.h>
12#include <context_mgmt.h>
13#include <debug.h>
14#include <platform_def.h>
15#include <platform.h>
16#include <secure_partition.h>
17#include <string.h>
18#include <types.h>
19#include <xlat_tables_v2.h>
20
21#include "spm_private.h"
22#include "spm_shim_private.h"
23
Antonio Nino Diaz086fbd62017-11-17 11:48:55 +000024/* Place translation tables by default along with the ones used by BL31. */
25#ifndef PLAT_SP_IMAGE_XLAT_SECTION_NAME
26#define PLAT_SP_IMAGE_XLAT_SECTION_NAME "xlat_table"
27#endif
28
Antonio Nino Diazc41f2062017-10-24 10:07:35 +010029/* Allocate and initialise the translation context for the secure partition. */
30REGISTER_XLAT_CONTEXT2(secure_partition,
31 PLAT_SP_IMAGE_MMAP_REGIONS,
32 PLAT_SP_IMAGE_MAX_XLAT_TABLES,
33 PLAT_VIRT_ADDR_SPACE_SIZE, PLAT_PHY_ADDR_SPACE_SIZE,
Antonio Nino Diaz086fbd62017-11-17 11:48:55 +000034 EL1_EL0_REGIME, PLAT_SP_IMAGE_XLAT_SECTION_NAME);
Antonio Nino Diazc41f2062017-10-24 10:07:35 +010035
36/* Export a handle on the secure partition translation context */
37xlat_ctx_t *secure_partition_xlat_ctx_handle = &secure_partition_xlat_ctx;
38
39/* Setup context of the Secure Partition */
40void secure_partition_setup(void)
41{
42 VERBOSE("S-EL1/S-EL0 context setup start...\n");
43
44 cpu_context_t *ctx = cm_get_context(SECURE);
45
46 /* Make sure that we got a Secure context. */
47 assert(ctx != NULL);
48
49 /* Assert we are in Secure state. */
50 assert((read_scr_el3() & SCR_NS_BIT) == 0);
51
52 /* Disable MMU at EL1. */
53 disable_mmu_icache_el1();
54
55 /* Invalidate TLBs at EL1. */
56 tlbivmalle1();
Antonio Nino Diazeb24dff2018-02-19 13:53:48 +000057 dsbish();
Antonio Nino Diazc41f2062017-10-24 10:07:35 +010058
59 /*
60 * General-Purpose registers
61 * -------------------------
62 */
63
64 /*
65 * X0: Virtual address of a buffer shared between EL3 and Secure EL0.
66 * The buffer will be mapped in the Secure EL1 translation regime
67 * with Normal IS WBWA attributes and RO data and Execute Never
68 * instruction access permissions.
69 *
70 * X1: Size of the buffer in bytes
71 *
72 * X2: cookie value (Implementation Defined)
73 *
74 * X3: cookie value (Implementation Defined)
75 *
76 * X4 to X30 = 0 (already done by cm_init_my_context())
77 */
78 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X0, PLAT_SPM_BUF_BASE);
79 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X1, PLAT_SPM_BUF_SIZE);
80 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X2, PLAT_SPM_COOKIE_0);
81 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X3, PLAT_SPM_COOKIE_1);
82
83 /*
84 * SP_EL0: A non-zero value will indicate to the SP that the SPM has
85 * initialized the stack pointer for the current CPU through
86 * implementation defined means. The value will be 0 otherwise.
87 */
88 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_SP_EL0,
89 PLAT_SP_IMAGE_STACK_BASE + PLAT_SP_IMAGE_STACK_PCPU_SIZE);
90
91 /*
92 * Setup translation tables
93 * ------------------------
94 */
95
96#if ENABLE_ASSERTIONS
97
98 /* Get max granularity supported by the platform. */
99
Antonio Nino Diaz097e2e12017-11-14 13:41:27 +0000100 u_register_t id_aa64mmfr0_el1 = read_id_aa64mmfr0_el1();
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100101
102 int tgran64_supported =
Antonio Nino Diaz097e2e12017-11-14 13:41:27 +0000103 ((id_aa64mmfr0_el1 >> ID_AA64MMFR0_EL1_TGRAN64_SHIFT) &
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100104 ID_AA64MMFR0_EL1_TGRAN64_MASK) ==
105 ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED;
106
107 int tgran16_supported =
Antonio Nino Diaz097e2e12017-11-14 13:41:27 +0000108 ((id_aa64mmfr0_el1 >> ID_AA64MMFR0_EL1_TGRAN16_SHIFT) &
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100109 ID_AA64MMFR0_EL1_TGRAN16_MASK) ==
110 ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED;
111
112 int tgran4_supported =
Antonio Nino Diaz097e2e12017-11-14 13:41:27 +0000113 ((id_aa64mmfr0_el1 >> ID_AA64MMFR0_EL1_TGRAN4_SHIFT) &
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100114 ID_AA64MMFR0_EL1_TGRAN4_MASK) ==
115 ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED;
116
117 uintptr_t max_granule_size;
118
119 if (tgran64_supported) {
120 max_granule_size = 64 * 1024;
121 } else if (tgran16_supported) {
122 max_granule_size = 16 * 1024;
123 } else {
124 assert(tgran4_supported);
125 max_granule_size = 4 * 1024;
126 }
127
128 VERBOSE("Max translation granule supported: %lu KiB\n",
Antonio Nino Diaz097e2e12017-11-14 13:41:27 +0000129 max_granule_size / 1024);
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100130
131 uintptr_t max_granule_size_mask = max_granule_size - 1;
132
133 /* Base must be aligned to the max granularity */
134 assert((ARM_SP_IMAGE_NS_BUF_BASE & max_granule_size_mask) == 0);
135
136 /* Size must be a multiple of the max granularity */
137 assert((ARM_SP_IMAGE_NS_BUF_SIZE & max_granule_size_mask) == 0);
138
139#endif /* ENABLE_ASSERTIONS */
140
141 /* This region contains the exception vectors used at S-EL1. */
142 const mmap_region_t sel1_exception_vectors =
143 MAP_REGION_FLAT(SPM_SHIM_EXCEPTIONS_START,
144 SPM_SHIM_EXCEPTIONS_SIZE,
145 MT_CODE | MT_SECURE | MT_PRIVILEGED);
146 mmap_add_region_ctx(&secure_partition_xlat_ctx,
147 &sel1_exception_vectors);
148
149 mmap_add_ctx(&secure_partition_xlat_ctx,
150 plat_get_secure_partition_mmap(NULL));
151
152 init_xlat_tables_ctx(&secure_partition_xlat_ctx);
153
154 /*
155 * MMU-related registers
156 * ---------------------
157 */
158
159 /* Set attributes in the right indices of the MAIR */
160 u_register_t mair_el1 =
161 MAIR_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX) |
162 MAIR_ATTR_SET(ATTR_IWBWA_OWBWA_NTR, ATTR_IWBWA_OWBWA_NTR_INDEX) |
163 MAIR_ATTR_SET(ATTR_NON_CACHEABLE, ATTR_NON_CACHEABLE_INDEX);
164
165 write_ctx_reg(get_sysregs_ctx(ctx), CTX_MAIR_EL1, mair_el1);
166
167 /* Setup TCR_EL1. */
168 u_register_t tcr_ps_bits = tcr_physical_addr_size_bits(PLAT_PHY_ADDR_SPACE_SIZE);
169
170 u_register_t tcr_el1 =
171 /* Size of region addressed by TTBR0_EL1 = 2^(64-T0SZ) bytes. */
172 (64 - __builtin_ctzl(PLAT_VIRT_ADDR_SPACE_SIZE)) |
173 /* Inner and outer WBWA, shareable. */
174 TCR_SH_INNER_SHAREABLE | TCR_RGN_OUTER_WBA | TCR_RGN_INNER_WBA |
175 /* Set the granularity to 4KB. */
176 TCR_TG0_4K |
177 /* Limit Intermediate Physical Address Size. */
178 tcr_ps_bits << TCR_EL1_IPS_SHIFT |
179 /* Disable translations using TBBR1_EL1. */
180 TCR_EPD1_BIT
181 /* The remaining fields related to TBBR1_EL1 are left as zero. */
182 ;
183
184 tcr_el1 &= ~(
185 /* Enable translations using TBBR0_EL1 */
186 TCR_EPD0_BIT
187 );
188
189 write_ctx_reg(get_sysregs_ctx(ctx), CTX_TCR_EL1, tcr_el1);
190
191 /* Setup SCTLR_EL1 */
192 u_register_t sctlr_el1 = read_ctx_reg(get_sysregs_ctx(ctx), CTX_SCTLR_EL1);
193
194 sctlr_el1 |=
195 /*SCTLR_EL1_RES1 |*/
196 /* Don't trap DC CVAU, DC CIVAC, DC CVAC, DC CVAP, or IC IVAU */
197 SCTLR_UCI_BIT |
198 /* RW regions at xlat regime EL1&0 are forced to be XN. */
199 SCTLR_WXN_BIT |
200 /* Don't trap to EL1 execution of WFI or WFE at EL0. */
201 SCTLR_NTWI_BIT | SCTLR_NTWE_BIT |
202 /* Don't trap to EL1 accesses to CTR_EL0 from EL0. */
203 SCTLR_UCT_BIT |
204 /* Don't trap to EL1 execution of DZ ZVA at EL0. */
205 SCTLR_DZE_BIT |
206 /* Enable SP Alignment check for EL0 */
207 SCTLR_SA0_BIT |
208 /* Allow cacheable data and instr. accesses to normal memory. */
209 SCTLR_C_BIT | SCTLR_I_BIT |
210 /* Alignment fault checking enabled when at EL1 and EL0. */
211 SCTLR_A_BIT |
212 /* Enable MMU. */
213 SCTLR_M_BIT
214 ;
215
216 sctlr_el1 &= ~(
217 /* Explicit data accesses at EL0 are little-endian. */
218 SCTLR_E0E_BIT |
219 /* Accesses to DAIF from EL0 are trapped to EL1. */
220 SCTLR_UMA_BIT
221 );
222
223 write_ctx_reg(get_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_el1);
224
225 /* Point TTBR0_EL1 at the tables of the context created for the SP. */
226 write_ctx_reg(get_sysregs_ctx(ctx), CTX_TTBR0_EL1,
227 (u_register_t)secure_partition_base_xlat_table);
228
229 /*
230 * Setup other system registers
231 * ----------------------------
232 */
233
234 /* Shim Exception Vector Base Address */
235 write_ctx_reg(get_sysregs_ctx(ctx), CTX_VBAR_EL1,
236 SPM_SHIM_EXCEPTIONS_PTR);
237
238 /*
239 * FPEN: Forbid the Secure Partition to access FP/SIMD registers.
240 * TTA: Enable access to trace registers.
241 * ZEN (v8.2): Trap SVE instructions and access to SVE registers.
242 */
243 write_ctx_reg(get_sysregs_ctx(ctx), CTX_CPACR_EL1,
244 CPACR_EL1_FPEN(CPACR_EL1_FP_TRAP_ALL));
245
246 /*
247 * Prepare information in buffer shared between EL3 and S-EL0
248 * ----------------------------------------------------------
249 */
250
251 void *shared_buf_ptr = (void *) PLAT_SPM_BUF_BASE;
252
253 /* Copy the boot information into the shared buffer with the SP. */
254 assert((uintptr_t)shared_buf_ptr + sizeof(secure_partition_boot_info_t)
255 <= (PLAT_SPM_BUF_BASE + PLAT_SPM_BUF_SIZE));
256
257 assert(PLAT_SPM_BUF_BASE <= (UINTPTR_MAX - PLAT_SPM_BUF_SIZE + 1));
258
259 const secure_partition_boot_info_t *sp_boot_info =
260 plat_get_secure_partition_boot_info(NULL);
261
262 assert(sp_boot_info != NULL);
263
264 memcpy((void *) shared_buf_ptr, (const void *) sp_boot_info,
265 sizeof(secure_partition_boot_info_t));
266
267 /* Pointer to the MP information from the platform port. */
268 secure_partition_mp_info_t *sp_mp_info =
269 ((secure_partition_boot_info_t *) shared_buf_ptr)->mp_info;
270
271 assert(sp_mp_info != NULL);
272
273 /*
274 * Point the shared buffer MP information pointer to where the info will
275 * be populated, just after the boot info.
276 */
277 ((secure_partition_boot_info_t *) shared_buf_ptr)->mp_info =
Antonio Nino Diaz0dcebaf2017-11-10 12:25:49 +0000278 (secure_partition_mp_info_t *) ((uintptr_t)shared_buf_ptr
279 + sizeof(secure_partition_boot_info_t));
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100280
281 /*
282 * Update the shared buffer pointer to where the MP information for the
283 * payload will be populated
284 */
285 shared_buf_ptr = ((secure_partition_boot_info_t *) shared_buf_ptr)->mp_info;
286
287 /*
288 * Copy the cpu information into the shared buffer area after the boot
289 * information.
290 */
291 assert(sp_boot_info->num_cpus <= PLATFORM_CORE_COUNT);
292
293 assert((uintptr_t)shared_buf_ptr
294 <= (PLAT_SPM_BUF_BASE + PLAT_SPM_BUF_SIZE -
295 (sp_boot_info->num_cpus * sizeof(*sp_mp_info))));
296
297 memcpy(shared_buf_ptr, (const void *) sp_mp_info,
298 sp_boot_info->num_cpus * sizeof(*sp_mp_info));
299
300 /*
301 * Calculate the linear indices of cores in boot information for the
302 * secure partition and flag the primary CPU
303 */
304 sp_mp_info = (secure_partition_mp_info_t *) shared_buf_ptr;
305
306 for (unsigned int index = 0; index < sp_boot_info->num_cpus; index++) {
307 u_register_t mpidr = sp_mp_info[index].mpidr;
308
309 sp_mp_info[index].linear_id = plat_core_pos_by_mpidr(mpidr);
310 if (plat_my_core_pos() == sp_mp_info[index].linear_id)
311 sp_mp_info[index].flags |= MP_INFO_FLAG_PRIMARY_CPU;
312 }
313
314 VERBOSE("S-EL1/S-EL0 context setup end.\n");
315}