| Andre Przywara | 8be92f3 | 2022-12-08 00:41:07 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef SUNXI_CPUCFG_H |
| 8 | #define SUNXI_CPUCFG_H |
| 9 | |
| 10 | #include <sunxi_mmap.h> |
| 11 | |
| 12 | /* c = cluster, n = core */ |
| 13 | #define SUNXI_CPUCFG_CLS_CTRL_REG0(c) (SUNXI_CPUCFG_BASE + 0x0010 + (c) * 0x10) |
| 14 | #define SUNXI_CPUCFG_CLS_CTRL_REG1(c) (SUNXI_CPUCFG_BASE + 0x0014 + (c) * 0x10) |
| 15 | #define SUNXI_CPUCFG_CACHE_CFG_REG (SUNXI_CPUCFG_BASE + 0x0024) |
| Mikhail Kalashnikov | 7604baf | 2022-12-09 01:56:20 +0000 | [diff] [blame] | 16 | /* The T507 datasheet does not mention this register. */ |
| Andre Przywara | 8be92f3 | 2022-12-08 00:41:07 +0000 | [diff] [blame] | 17 | #define SUNXI_CPUCFG_DBG_REG0 (SUNXI_CPUCFG_BASE + 0x00c0) |
| 18 | |
| 19 | #define SUNXI_CPUCFG_RST_CTRL_REG(c) (SUNXI_CPUCFG_BASE + 0x0000 + (c) * 4) |
| 20 | #define SUNXI_CPUCFG_RVBAR_LO_REG(n) (SUNXI_CPUCFG_BASE + 0x0040 + (n) * 8) |
| 21 | #define SUNXI_CPUCFG_RVBAR_HI_REG(n) (SUNXI_CPUCFG_BASE + 0x0044 + (n) * 8) |
| 22 | |
| Mikhail Kalashnikov | 7604baf | 2022-12-09 01:56:20 +0000 | [diff] [blame] | 23 | #define SUNXI_C0_CPU_CTRL_REG(n) (SUNXI_CPUCFG_BASE + 0x0060 + (n) * 4) |
| 24 | |
| 25 | #define SUNXI_CPU_CTRL_REG(n) (SUNXI_CPUSUBSYS_BASE + 0x20 + (n) * 4) |
| 26 | #define SUNXI_ALT_RVBAR_LO_REG(n) (SUNXI_CPUSUBSYS_BASE + 0x40 + (n) * 8) |
| 27 | #define SUNXI_ALT_RVBAR_HI_REG(n) (SUNXI_CPUSUBSYS_BASE + 0x44 + (n) * 8) |
| 28 | |
| Andre Przywara | 8be92f3 | 2022-12-08 00:41:07 +0000 | [diff] [blame] | 29 | #define SUNXI_POWERON_RST_REG(c) (SUNXI_R_CPUCFG_BASE + 0x0040 + (c) * 4) |
| 30 | #define SUNXI_POWEROFF_GATING_REG(c) (SUNXI_R_CPUCFG_BASE + 0x0044 + (c) * 4) |
| 31 | #define SUNXI_CPU_POWER_CLAMP_REG(c, n) (SUNXI_R_CPUCFG_BASE + 0x0050 + \ |
| 32 | (c) * 0x10 + (n) * 4) |
| Mikhail Kalashnikov | 7604baf | 2022-12-09 01:56:20 +0000 | [diff] [blame] | 33 | #define SUNXI_CPU_UNK_REG(n) (SUNXI_R_CPUCFG_BASE + 0x0070 + (n) * 4) |
| Andre Przywara | 8be92f3 | 2022-12-08 00:41:07 +0000 | [diff] [blame] | 34 | |
| 35 | #define SUNXI_CPUIDLE_EN_REG (SUNXI_R_CPUCFG_BASE + 0x0100) |
| 36 | #define SUNXI_CORE_CLOSE_REG (SUNXI_R_CPUCFG_BASE + 0x0104) |
| 37 | #define SUNXI_PWR_SW_DELAY_REG (SUNXI_R_CPUCFG_BASE + 0x0140) |
| 38 | #define SUNXI_CONFIG_DELAY_REG (SUNXI_R_CPUCFG_BASE + 0x0144) |
| 39 | |
| 40 | #define SUNXI_AA64nAA32_REG SUNXI_CPUCFG_CLS_CTRL_REG0 |
| 41 | #define SUNXI_AA64nAA32_OFFSET 24 |
| 42 | |
| 43 | #endif /* SUNXI_CPUCFG_H */ |