| Bipin Ravi | 4da1b0b | 2021-03-16 15:20:58 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2021, Arm Limited. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
| 8 | #include <asm_macros.S> |
| 9 | #include <common/bl_common.h> |
| 10 | #include <cortex_a78c.h> |
| 11 | #include <cpu_macros.S> |
| 12 | #include <plat_macros.S> |
| 13 | |
| 14 | /* Hardware handled coherency */ |
| 15 | #if HW_ASSISTED_COHERENCY == 0 |
| 16 | #error "cortex_a78c must be compiled with HW_ASSISTED_COHERENCY enabled" |
| 17 | #endif |
| 18 | |
| 19 | /* ---------------------------------------------------- |
| 20 | * HW will do the cache maintenance while powering down |
| 21 | * ---------------------------------------------------- |
| 22 | */ |
| 23 | func cortex_a78c_core_pwr_dwn |
| 24 | /* --------------------------------------------------- |
| 25 | * Enable CPU power down bit in power control register |
| 26 | * --------------------------------------------------- |
| 27 | */ |
| 28 | mrs x0, CORTEX_A78C_CPUPWRCTLR_EL1 |
| 29 | orr x0, x0, #CORTEX_A78C_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT |
| 30 | msr CORTEX_A78C_CPUPWRCTLR_EL1, x0 |
| 31 | isb |
| 32 | ret |
| 33 | endfunc cortex_a78c_core_pwr_dwn |
| 34 | |
| 35 | #if REPORT_ERRATA |
| 36 | /* |
| 37 | * Errata printing function for Cortex A78C. Must follow AAPCS. |
| 38 | */ |
| 39 | func cortex_a78c_errata_report |
| 40 | ret |
| 41 | endfunc cortex_a78c_errata_report |
| 42 | #endif |
| 43 | |
| 44 | /* --------------------------------------------- |
| 45 | * This function provides cortex_a78c specific |
| 46 | * register information for crash reporting. |
| 47 | * It needs to return with x6 pointing to |
| 48 | * a list of register names in ascii and |
| 49 | * x8 - x15 having values of registers to be |
| 50 | * reported. |
| 51 | * --------------------------------------------- |
| 52 | */ |
| 53 | .section .rodata.cortex_a78c_regs, "aS" |
| 54 | cortex_a78c_regs: /* The ascii list of register names to be reported */ |
| 55 | .asciz "cpuectlr_el1", "" |
| 56 | |
| 57 | func cortex_a78c_cpu_reg_dump |
| 58 | adr x6, cortex_a78c_regs |
| 59 | mrs x8, CORTEX_A78C_CPUECTLR_EL1 |
| 60 | ret |
| 61 | endfunc cortex_a78c_cpu_reg_dump |
| 62 | |
| 63 | declare_cpu_ops cortex_a78c, CORTEX_A78C_MIDR, \ |
| 64 | CPU_NO_RESET_FUNC, \ |
| 65 | cortex_a78c_core_pwr_dwn |