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Andre Przywara6d471e12019-07-09 11:25:57 +01001/*
2 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <assert.h>
8
9#include <libfdt.h>
10
11#include <platform_def.h>
Andre Przywara88c9e1d2019-07-11 01:45:39 +010012#include <arch_helpers.h>
Andre Przywara6d471e12019-07-09 11:25:57 +010013#include <common/bl_common.h>
14#include <lib/mmio.h>
15#include <lib/xlat_tables/xlat_mmu_helpers.h>
16#include <lib/xlat_tables/xlat_tables_defs.h>
Andre Przywara2d8e99a2019-07-10 18:09:18 +010017#include <lib/xlat_tables/xlat_tables_v2.h>
Andre Przywara6d471e12019-07-09 11:25:57 +010018#include <plat/common/platform.h>
Andre Przywara88c9e1d2019-07-11 01:45:39 +010019#include <common/fdt_fixup.h>
Andre Przywara97c6e902020-07-09 12:33:17 +010020#include <common/fdt_wrappers.h>
Andre Przywara88c9e1d2019-07-11 01:45:39 +010021#include <libfdt.h>
Andre Przywara6d471e12019-07-09 11:25:57 +010022
23#include <drivers/arm/gicv2.h>
24
25#include <rpi_shared.h>
26
Andre Przywara2d8e99a2019-07-10 18:09:18 +010027/*
28 * Fields at the beginning of armstub8.bin.
29 * While building the BL31 image, we put the stub magic into the binary.
30 * The GPU firmware detects this at boot time, clears that field as a
31 * confirmation and puts the kernel and DT address in the following words.
32 */
33extern uint32_t stub_magic;
Andre Przywaraaa89ae42019-07-11 01:42:12 +010034extern uint32_t dtb_ptr32;
35extern uint32_t kernel_entry32;
Andre Przywara2d8e99a2019-07-10 18:09:18 +010036
Andre Przywara6d471e12019-07-09 11:25:57 +010037static const gicv2_driver_data_t rpi4_gic_data = {
38 .gicd_base = RPI4_GIC_GICD_BASE,
39 .gicc_base = RPI4_GIC_GICC_BASE,
40};
41
42/*
43 * To be filled by the code below. At the moment BL32 is not supported.
44 * In the future these might be passed down from BL2.
45 */
46static entry_point_info_t bl32_image_ep_info;
47static entry_point_info_t bl33_image_ep_info;
48
49/*******************************************************************************
50 * Return a pointer to the 'entry_point_info' structure of the next image for
51 * the security state specified. BL33 corresponds to the non-secure image type
52 * while BL32 corresponds to the secure image type. A NULL pointer is returned
53 * if the image does not exist.
54 ******************************************************************************/
55entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
56{
57 entry_point_info_t *next_image_info;
58
59 assert(sec_state_is_valid(type) != 0);
60
61 next_image_info = (type == NON_SECURE)
62 ? &bl33_image_ep_info : &bl32_image_ep_info;
63
64 /* None of the images can have 0x0 as the entrypoint. */
65 if (next_image_info->pc) {
66 return next_image_info;
67 } else {
68 return NULL;
69 }
70}
71
Andre Przywaraaa89ae42019-07-11 01:42:12 +010072uintptr_t plat_get_ns_image_entrypoint(void)
73{
74#ifdef PRELOADED_BL33_BASE
75 return PRELOADED_BL33_BASE;
76#else
77 /* Cleared by the GPU if kernel address is valid. */
78 if (stub_magic == 0)
79 return kernel_entry32;
80
81 WARN("Stub magic failure, using default kernel address 0x80000\n");
82 return 0x80000;
83#endif
84}
85
86static uintptr_t rpi4_get_dtb_address(void)
87{
88#ifdef RPI3_PRELOADED_DTB_BASE
89 return RPI3_PRELOADED_DTB_BASE;
90#else
91 /* Cleared by the GPU if DTB address is valid. */
92 if (stub_magic == 0)
93 return dtb_ptr32;
94
95 WARN("Stub magic failure, DTB address unknown\n");
96 return 0;
97#endif
98}
99
Andre Przywara6d471e12019-07-09 11:25:57 +0100100static void ldelay(register_t delay)
101{
102 __asm__ volatile (
103 "1:\tcbz %0, 2f\n\t"
104 "sub %0, %0, #1\n\t"
105 "b 1b\n"
106 "2:"
107 : "=&r" (delay) : "0" (delay)
108 );
109}
110
111/*******************************************************************************
112 * Perform any BL31 early platform setup. Here is an opportunity to copy
113 * parameters passed by the calling EL (S-EL1 in BL2 & EL3 in BL1) before
114 * they are lost (potentially). This needs to be done before the MMU is
115 * initialized so that the memory layout can be used while creating page
116 * tables. BL2 has flushed this information to memory, so we are guaranteed
117 * to pick up good data.
118 ******************************************************************************/
119void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
120 u_register_t arg2, u_register_t arg3)
121
122{
Andre Przywara6d471e12019-07-09 11:25:57 +0100123 /*
124 * LOCAL_CONTROL:
125 * Bit 9 clear: Increment by 1 (vs. 2).
126 * Bit 8 clear: Timer source is 19.2MHz crystal (vs. APB).
127 */
128 mmio_write_32(RPI4_LOCAL_CONTROL_BASE_ADDRESS, 0);
129
130 /* LOCAL_PRESCALER; divide-by (0x80000000 / register_val) == 1 */
131 mmio_write_32(RPI4_LOCAL_CONTROL_PRESCALER, 0x80000000);
132
133 /* Early GPU firmware revisions need a little break here. */
134 ldelay(100000);
135
Andre Przywara57ccecc2020-03-10 12:33:16 +0000136 /* Initialize the console to provide early debug support. */
137 rpi3_console_init();
Andre Przywara6d471e12019-07-09 11:25:57 +0100138
Andre Przywara6d471e12019-07-09 11:25:57 +0100139 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
Andre Przywaraaa89ae42019-07-11 01:42:12 +0100140 bl33_image_ep_info.spsr = rpi3_get_spsr_for_bl33_entry();
Andre Przywara6d471e12019-07-09 11:25:57 +0100141 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
142
Andre Przywaraaa89ae42019-07-11 01:42:12 +0100143#if RPI3_DIRECT_LINUX_BOOT
Andre Przywara6d471e12019-07-09 11:25:57 +0100144# if RPI3_BL33_IN_AARCH32
145 /*
146 * According to the file ``Documentation/arm/Booting`` of the Linux
147 * kernel tree, Linux expects:
148 * r0 = 0
149 * r1 = machine type number, optional in DT-only platforms (~0 if so)
150 * r2 = Physical address of the device tree blob
151 */
152 VERBOSE("rpi4: Preparing to boot 32-bit Linux kernel\n");
153 bl33_image_ep_info.args.arg0 = 0U;
154 bl33_image_ep_info.args.arg1 = ~0U;
Andre Przywaraaa89ae42019-07-11 01:42:12 +0100155 bl33_image_ep_info.args.arg2 = rpi4_get_dtb_address();
Andre Przywara6d471e12019-07-09 11:25:57 +0100156# else
157 /*
158 * According to the file ``Documentation/arm64/booting.txt`` of the
159 * Linux kernel tree, Linux expects the physical address of the device
160 * tree blob (DTB) in x0, while x1-x3 are reserved for future use and
161 * must be 0.
162 */
163 VERBOSE("rpi4: Preparing to boot 64-bit Linux kernel\n");
Andre Przywaraaa89ae42019-07-11 01:42:12 +0100164 bl33_image_ep_info.args.arg0 = rpi4_get_dtb_address();
Andre Przywara6d471e12019-07-09 11:25:57 +0100165 bl33_image_ep_info.args.arg1 = 0ULL;
166 bl33_image_ep_info.args.arg2 = 0ULL;
167 bl33_image_ep_info.args.arg3 = 0ULL;
168# endif /* RPI3_BL33_IN_AARCH32 */
169#endif /* RPI3_DIRECT_LINUX_BOOT */
170}
171
172void bl31_plat_arch_setup(void)
173{
Andre Przywara2d8e99a2019-07-10 18:09:18 +0100174 /*
Andre Przywara88c9e1d2019-07-11 01:45:39 +0100175 * Is the dtb_ptr32 pointer valid? If yes, map the DTB region.
176 * We map the 2MB region the DTB start address lives in, plus
177 * the next 2MB, to have enough room for expansion.
178 */
179 if (stub_magic == 0) {
180 unsigned long long dtb_region = dtb_ptr32;
181
182 dtb_region &= ~0x1fffff; /* Align to 2 MB. */
183 mmap_add_region(dtb_region, dtb_region, 4U << 20,
184 MT_MEMORY | MT_RW | MT_NS);
185 }
186 /*
Andre Przywara2d8e99a2019-07-10 18:09:18 +0100187 * Add the first page of memory, which holds the stub magic,
188 * the kernel and the DT address.
Andre Przywara8b83a512019-07-15 09:04:27 +0100189 * This also holds the secondary CPU's entrypoints and mailboxes.
Andre Przywara2d8e99a2019-07-10 18:09:18 +0100190 */
Andre Przywara8b83a512019-07-15 09:04:27 +0100191 mmap_add_region(0, 0, 4096, MT_NON_CACHEABLE | MT_RW | MT_SECURE);
Andre Przywara2d8e99a2019-07-10 18:09:18 +0100192
Andre Przywara6d471e12019-07-09 11:25:57 +0100193 rpi3_setup_page_tables(BL31_BASE, BL31_END - BL31_BASE,
194 BL_CODE_BASE, BL_CODE_END,
195 BL_RO_DATA_BASE, BL_RO_DATA_END
196#if USE_COHERENT_MEM
197 , BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END
198#endif
199 );
200
201 enable_mmu_el3(0);
202}
203
Andre Przywara88c9e1d2019-07-11 01:45:39 +0100204static void rpi4_prepare_dtb(void)
205{
206 void *dtb = (void *)rpi4_get_dtb_address();
Andre Przywara88ac8b62019-07-21 01:45:31 +0100207 uint32_t gic_int_prop[3];
208 int ret, offs;
Andre Przywara88c9e1d2019-07-11 01:45:39 +0100209
210 /* Return if no device tree is detected */
211 if (fdt_check_header(dtb) != 0)
212 return;
213
214 ret = fdt_open_into(dtb, dtb, 0x100000);
215 if (ret < 0) {
216 ERROR("Invalid Device Tree at %p: error %d\n", dtb, ret);
217 return;
218 }
219
220 if (dt_add_psci_node(dtb)) {
221 ERROR("Failed to add PSCI Device Tree node\n");
222 return;
223 }
224
225 if (dt_add_psci_cpu_enable_methods(dtb)) {
226 ERROR("Failed to add PSCI cpu enable methods in Device Tree\n");
227 return;
228 }
229
Andre Przywaraaf7df712019-07-22 00:04:40 +0100230 /* Reserve memory used by Trusted Firmware. */
231 if (fdt_add_reserved_memory(dtb, "atf@0", 0, 0x80000))
232 WARN("Failed to add reserved memory nodes to DT.\n");
233
Andre Przywara88ac8b62019-07-21 01:45:31 +0100234 offs = fdt_node_offset_by_compatible(dtb, 0, "arm,gic-400");
235 gic_int_prop[0] = cpu_to_fdt32(1); // PPI
236 gic_int_prop[1] = cpu_to_fdt32(9); // PPI #9
237 gic_int_prop[2] = cpu_to_fdt32(0x0f04); // all cores, level high
238 fdt_setprop(dtb, offs, "interrupts", gic_int_prop, 12);
239
Andre Przywara48a52912019-07-15 18:07:51 +0100240 offs = fdt_path_offset(dtb, "/chosen");
241 fdt_setprop_string(dtb, offs, "stdout-path", "serial0");
242
Andre Przywara88c9e1d2019-07-11 01:45:39 +0100243 ret = fdt_pack(dtb);
244 if (ret < 0)
245 ERROR("Failed to pack Device Tree at %p: error %d\n", dtb, ret);
246
Andre Przywara97c6e902020-07-09 12:33:17 +0100247 clean_dcache_range((uintptr_t)dtb, fdt_blob_size(dtb));
Andre Przywara88c9e1d2019-07-11 01:45:39 +0100248 INFO("Changed device tree to advertise PSCI.\n");
249}
250
Andre Przywara6d471e12019-07-09 11:25:57 +0100251void bl31_platform_setup(void)
252{
Andre Przywara88c9e1d2019-07-11 01:45:39 +0100253 rpi4_prepare_dtb();
254
Andre Przywara6d471e12019-07-09 11:25:57 +0100255 /* Configure the interrupt controller */
256 gicv2_driver_init(&rpi4_gic_data);
257 gicv2_distif_init();
258 gicv2_pcpu_distif_init();
259 gicv2_cpuif_enable();
260}