| Pankaj Gupta | adbc3fa | 2020-12-09 14:02:39 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2021 NXP |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | * |
| 6 | */ |
| 7 | |
| 8 | #ifndef PMU_H |
| 9 | #define PMU_H |
| 10 | |
| 11 | /* PMU Registers' OFFSET */ |
| 12 | #define PMU_PCPW20SR_OFFSET 0x830 |
| 13 | #define PMU_CLL2FLUSHSETR_OFFSET 0x1110 |
| 14 | #define PMU_CLSL2FLUSHCLRR_OFFSET 0x1114 |
| 15 | #define PMU_CLL2FLUSHSR_OFFSET 0x1118 |
| 16 | #define PMU_POWMGTCSR_VAL (1 << 20) |
| 17 | |
| 18 | /* PMU Registers */ |
| 19 | #define CORE_TIMEBASE_ENBL_OFFSET 0x8A0 |
| 20 | #define CLUST_TIMER_BASE_ENBL_OFFSET 0x18A0 |
| 21 | |
| 22 | #define PMU_IDLE_CLUSTER_MASK 0x2 |
| 23 | #define PMU_FLUSH_CLUSTER_MASK 0x2 |
| 24 | #define PMU_IDLE_CORE_MASK 0xfe |
| 25 | |
| 26 | /* pmu register offsets and bitmaps */ |
| 27 | #define PMU_POWMGTDCR0_OFFSET 0xC20 |
| 28 | #define PMU_POWMGTCSR_OFFSET 0x4000 |
| 29 | #define PMU_CLAINACTSETR_OFFSET 0x1100 |
| 30 | #define PMU_CLAINACTCLRR_OFFSET 0x1104 |
| 31 | #define PMU_CLSINACTSETR_OFFSET 0x1108 |
| 32 | #define PMU_CLSINACTCLRR_OFFSET 0x110C |
| 33 | #define PMU_CLL2FLUSHSETR_OFFSET 0x1110 |
| 34 | #define PMU_CLL2FLUSHCLRR_OFFSET 0x1114 |
| 35 | #define PMU_IPPDEXPCR0_OFFSET 0x4040 |
| 36 | #define PMU_IPPDEXPCR1_OFFSET 0x4044 |
| 37 | #define PMU_IPPDEXPCR2_OFFSET 0x4048 |
| 38 | #define PMU_IPPDEXPCR3_OFFSET 0x404C |
| 39 | #define PMU_IPPDEXPCR4_OFFSET 0x4050 |
| 40 | #define PMU_IPPDEXPCR5_OFFSET 0x4054 |
| 41 | #define PMU_IPPDEXPCR6_OFFSET 0x4058 |
| 42 | #define PMU_IPSTPCR0_OFFSET 0x4120 |
| 43 | #define PMU_IPSTPCR1_OFFSET 0x4124 |
| 44 | #define PMU_IPSTPCR2_OFFSET 0x4128 |
| 45 | #define PMU_IPSTPCR3_OFFSET 0x412C |
| 46 | #define PMU_IPSTPCR4_OFFSET 0x4130 |
| 47 | #define PMU_IPSTPCR5_OFFSET 0x4134 |
| 48 | #define PMU_IPSTPCR6_OFFSET 0x4138 |
| 49 | #define PMU_IPSTPACKSR0_OFFSET 0x4140 |
| 50 | #define PMU_IPSTPACKSR1_OFFSET 0x4144 |
| 51 | #define PMU_IPSTPACKSR2_OFFSET 0x4148 |
| 52 | #define PMU_IPSTPACKSR3_OFFSET 0x414C |
| 53 | #define PMU_IPSTPACKSR4_OFFSET 0x4150 |
| 54 | #define PMU_IPSTPACKSR5_OFFSET 0x4154 |
| 55 | #define PMU_IPSTPACKSR6_OFFSET 0x4158 |
| 56 | |
| 57 | #define CLAINACT_DISABLE_ACP 0xFF |
| 58 | #define CLSINACT_DISABLE_SKY 0xFF |
| 59 | #define POWMGTDCR_STP_OV_EN 0x1 |
| 60 | #define POWMGTCSR_LPM20_REQ 0x00100000 |
| 61 | |
| 62 | /* Used by PMU */ |
| 63 | #define DEVDISR1_MASK 0x024F3504 |
| 64 | #define DEVDISR2_MASK 0x0003FFFF |
| 65 | #define DEVDISR3_MASK 0x0000303F |
| 66 | #define DEVDISR4_MASK 0x0000FFFF |
| 67 | #define DEVDISR5_MASK 0x00F07603 |
| 68 | #define DEVDISR6_MASK 0x00000001 |
| 69 | |
| 70 | #ifndef __ASSEMBLER__ |
| 71 | void enable_timer_base_to_cluster(uintptr_t nxp_pmu_addr); |
| 72 | void enable_core_tb(uintptr_t nxp_pmu_addr); |
| 73 | #endif /* __ASSEMBLER__ */ |
| 74 | |
| 75 | #endif |