blob: 161e2950f9dca6a66f5c02df710dab4ef78be505 [file] [log] [blame]
Pankaj Gupta74f7b142020-12-09 14:02:38 +05301/*
2 * Copyright 2018-2020 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 *
6 */
7
8#ifndef DCFG_H
9#define DCFG_H
10
11#include <endian.h>
12
13#if defined(CONFIG_CHASSIS_2)
14#include <dcfg_lsch2.h>
15#elif defined(CONFIG_CHASSIS_3_2)
16#include <dcfg_lsch3.h>
17#endif
18
19#ifdef NXP_GUR_BE
20#define gur_in32(a) bswap32(mmio_read_32((uintptr_t)(a)))
21#define gur_out32(a, v) mmio_write_32((uintptr_t)(a), bswap32(v))
22#elif defined(NXP_GUR_LE)
23#define gur_in32(a) mmio_read_32((uintptr_t)(a))
24#define gur_out32(a, v) mmio_write_32((uintptr_t)(a), v)
25#else
26#error Please define CCSR GUR register endianness
27#endif
28
29typedef struct {
30 bool is_populated;
31 uint8_t mfr_id;
32#if defined(CONFIG_CHASSIS_3_2)
33 uint8_t family;
34 uint8_t dev_id;
35#endif
36 uint8_t personality;
37 bool sec_enabled;
38 uint8_t maj_ver;
39 uint8_t min_ver;
40} soc_info_t;
41
42typedef struct {
43 bool is_populated;
44 uint8_t ocram_present;
45 uint8_t ddrc1_present;
46#if defined(CONFIG_CHASSIS_3_2)
47 uint8_t ddrc2_present;
48#endif
49} devdisr5_info_t;
50
51typedef struct {
52 uint32_t porsr1;
53 uintptr_t g_nxp_dcfg_addr;
54 unsigned long nxp_sysclk_freq;
55 unsigned long nxp_ddrclk_freq;
56 unsigned int nxp_plat_clk_divider;
57} dcfg_init_info_t;
58
59
60struct sysinfo {
61 unsigned long freq_platform;
62 unsigned long freq_ddr_pll0;
63 unsigned long freq_ddr_pll1;
64};
65
66int get_clocks(struct sysinfo *sys);
67
68/* Read the PORSR1 register */
69uint32_t read_reg_porsr1(void);
70
71/*******************************************************************************
72 * Returns true if secur eboot is enabled on board
73 * mode = 0 (development mode - sb_en = 1)
74 * mode = 1 (production mode - ITS = 1)
75 ******************************************************************************/
76bool check_boot_mode_secure(uint32_t *mode);
77
78const soc_info_t *get_soc_info();
79const devdisr5_info_t *get_devdisr5_info();
80
81void dcfg_init(dcfg_init_info_t *dcfg_init_data);
82bool is_sec_enabled(void);
83
84void error_handler(int error_code);
85#endif /* DCFG_H */