tony.xie | 54973e7 | 2017-04-24 16:18:10 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #ifndef __PMU_H__ |
| 32 | #define __PMU_H__ |
| 33 | |
| 34 | #include <soc.h> |
| 35 | |
| 36 | struct rk3328_sleep_ddr_data { |
| 37 | uint32_t pmu_debug_enable; |
| 38 | uint32_t debug_iomux_save; |
| 39 | uint32_t pmic_sleep_save; |
| 40 | uint32_t pmu_wakeup_conf0; |
| 41 | uint32_t pmu_pwrmd_com; |
| 42 | uint32_t cru_mode_save; |
| 43 | uint32_t clk_sel0, clk_sel1, clk_sel18, |
| 44 | clk_sel20, clk_sel24, clk_sel38; |
| 45 | uint32_t clk_ungt_save[CRU_CLKGATE_NUMS]; |
| 46 | uint32_t cru_plls_con_save[MAX_PLL][CRU_PLL_CON_NUMS]; |
| 47 | }; |
| 48 | |
| 49 | struct rk3328_sleep_sram_data { |
| 50 | uint32_t pmic_sleep_save; |
| 51 | uint32_t pmic_sleep_gpio_save[2]; |
| 52 | uint32_t ddr_grf_con0; |
| 53 | uint32_t dpll_con_save[CRU_PLL_CON_NUMS]; |
| 54 | uint32_t pd_sr_idle_save; |
| 55 | uint32_t uart2_ier; |
| 56 | }; |
| 57 | |
| 58 | /***************************************************************************** |
| 59 | * The ways of cores power domain contorlling |
| 60 | *****************************************************************************/ |
| 61 | enum cores_pm_ctr_mode { |
| 62 | core_pwr_pd = 0, |
| 63 | core_pwr_wfi = 1, |
| 64 | core_pwr_wfi_int = 2 |
| 65 | }; |
| 66 | |
| 67 | enum pmu_cores_pm_by_wfi { |
| 68 | core_pm_en = 0, |
| 69 | core_pm_int_wakeup_en, |
| 70 | core_pm_dis_int, |
| 71 | core_pm_sft_wakeup_en |
| 72 | }; |
| 73 | |
| 74 | extern void *pmu_cpuson_entrypoint_start; |
| 75 | extern void *pmu_cpuson_entrypoint_end; |
| 76 | extern uint64_t cpuson_entry_point[PLATFORM_CORE_COUNT]; |
| 77 | extern uint32_t cpuson_flags[PLATFORM_CORE_COUNT]; |
| 78 | |
| 79 | #define CORES_PM_DISABLE 0x0 |
| 80 | |
| 81 | /***************************************************************************** |
| 82 | * pmu con,reg |
| 83 | *****************************************************************************/ |
| 84 | #define PMU_WAKEUP_CFG0 0x00 |
| 85 | #define PMU_PWRDN_CON 0x0c |
| 86 | #define PMU_PWRDN_ST 0x10 |
| 87 | #define PMU_PWRMD_COM 0x18 |
| 88 | #define PMU_SFT_CON 0x1c |
| 89 | #define PMU_INT_CON 0x20 |
| 90 | #define PMU_INT_ST 0x24 |
| 91 | #define PMU_POWER_ST 0x44 |
| 92 | #define PMU_CPUAPM_CON(n) (0x80 + (n) * 4) |
| 93 | #define PMU_SYS_REG(n) (0xa0 + (n) * 4) |
| 94 | |
| 95 | #define CHECK_CPU_WFIE_BASE (GRF_BASE + GRF_CPU_STATUS(1)) |
| 96 | |
| 97 | enum pmu_core_pwrst_shift { |
| 98 | clst_cpu_wfe = 0, |
| 99 | clst_cpu_wfi = 4, |
| 100 | }; |
| 101 | |
| 102 | #define clstl_cpu_wfe (clst_cpu_wfe) |
| 103 | #define clstb_cpu_wfe (clst_cpu_wfe) |
| 104 | |
| 105 | enum pmu_pd_id { |
| 106 | PD_CPU0 = 0, |
| 107 | PD_CPU1, |
| 108 | PD_CPU2, |
| 109 | PD_CPU3, |
| 110 | }; |
| 111 | |
| 112 | enum pmu_power_mode_common { |
| 113 | pmu_mode_en = 0, |
| 114 | sref_enter_en, |
| 115 | global_int_disable_cfg, |
| 116 | cpu0_pd_en, |
| 117 | wait_wakeup_begin_cfg = 4, |
| 118 | l2_flush_en, |
| 119 | l2_idle_en, |
| 120 | ddrio_ret_de_req, |
| 121 | ddrio_ret_en = 8, |
| 122 | }; |
| 123 | |
| 124 | enum pmu_sft_con { |
| 125 | upctl_c_sysreq_cfg = 0, |
| 126 | l2flushreq_req, |
| 127 | ddr_io_ret_cfg, |
| 128 | pmu_sft_ret_cfg, |
| 129 | }; |
| 130 | |
| 131 | #define CKECK_WFE_MSK 0x1 |
| 132 | #define CKECK_WFI_MSK 0x10 |
| 133 | #define CKECK_WFEI_MSK 0x11 |
| 134 | |
| 135 | #define PD_CTR_LOOP 500 |
| 136 | #define CHK_CPU_LOOP 500 |
| 137 | #define MAX_WAIT_CONUT 1000 |
| 138 | |
| 139 | #define WAKEUP_INT_CLUSTER_EN 0x1 |
| 140 | #define PMIC_SLEEP_REG 0x34 |
| 141 | |
| 142 | #define PLL_IS_NORM_MODE(mode, pll_id) \ |
| 143 | ((mode & (PLL_NORM_MODE(pll_id)) & 0xffff) != 0) |
| 144 | |
| 145 | #define CTLR_ENABLE_G1_BIT BIT(1) |
| 146 | #define UART_FIFO_EMPTY BIT(6) |
| 147 | |
| 148 | #define UART_IER 0x04 |
| 149 | #define UART_FCR 0x08 |
| 150 | #define UART_LSR 0x14 |
| 151 | |
| 152 | #define UART_INT_DISABLE 0x00 |
| 153 | #define UART_FIFO_RESET 0x07 |
| 154 | |
| 155 | #endif /* __PMU_H__ */ |