Michal Simek | 9179436 | 2022-08-31 16:45:14 +0200 | [diff] [blame] | 1 | /* |
Michal Simek | 2a47faa | 2023-04-14 08:43:51 +0200 | [diff] [blame] | 2 | * Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. |
Michal Simek | 9179436 | 2022-08-31 16:45:14 +0200 | [diff] [blame] | 3 | * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. |
Akshay Belsare | 5303e3f | 2023-05-12 14:28:05 +0530 | [diff] [blame] | 4 | * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. |
Michal Simek | 9179436 | 2022-08-31 16:45:14 +0200 | [diff] [blame] | 5 | * |
| 6 | * SPDX-License-Identifier: BSD-3-Clause |
| 7 | */ |
| 8 | |
| 9 | #include <common/debug.h> |
| 10 | #include <common/runtime_svc.h> |
| 11 | #include <drivers/generic_delay_timer.h> |
| 12 | #include <lib/mmio.h> |
| 13 | #include <lib/xlat_tables/xlat_tables_v2.h> |
| 14 | #include <plat/common/platform.h> |
Akshay Belsare | 5303e3f | 2023-05-12 14:28:05 +0530 | [diff] [blame] | 15 | #include <plat_common.h> |
Michal Simek | aa5443e | 2022-09-19 14:04:55 +0200 | [diff] [blame] | 16 | #include <plat_ipi.h> |
Michal Simek | 9179436 | 2022-08-31 16:45:14 +0200 | [diff] [blame] | 17 | |
| 18 | #include <plat_private.h> |
| 19 | #include <versal_net_def.h> |
| 20 | |
| 21 | uint32_t platform_id, platform_version; |
| 22 | |
| 23 | /* |
| 24 | * Table of regions to map using the MMU. |
| 25 | * This doesn't include TZRAM as the 'mem_layout' argument passed to |
| 26 | * configure_mmu_elx() will give the available subset of that, |
| 27 | */ |
| 28 | const mmap_region_t plat_versal_net_mmap[] = { |
| 29 | MAP_REGION_FLAT(DEVICE0_BASE, DEVICE0_SIZE, MT_DEVICE | MT_RW | MT_SECURE), |
| 30 | MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW | MT_SECURE), |
| 31 | MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE, MT_DEVICE | MT_RW | MT_SECURE), |
| 32 | MAP_REGION_FLAT(CRF_BASE, CRF_SIZE, MT_DEVICE | MT_RW | MT_SECURE), |
Michal Simek | aa5443e | 2022-09-19 14:04:55 +0200 | [diff] [blame] | 33 | MAP_REGION_FLAT(IPI_BASE, IPI_SIZE, MT_DEVICE | MT_RW | MT_SECURE), |
Michal Simek | 9179436 | 2022-08-31 16:45:14 +0200 | [diff] [blame] | 34 | { 0 } |
| 35 | }; |
| 36 | |
Prasad Kummari | 0b37714 | 2023-10-26 16:32:26 +0530 | [diff] [blame] | 37 | const mmap_region_t *plat_get_mmap(void) |
Michal Simek | 9179436 | 2022-08-31 16:45:14 +0200 | [diff] [blame] | 38 | { |
| 39 | return plat_versal_net_mmap; |
| 40 | } |
| 41 | |
| 42 | /* For saving cpu clock for certain platform */ |
| 43 | uint32_t cpu_clock; |
| 44 | |
| 45 | char *board_name_decode(void) |
| 46 | { |
| 47 | switch (platform_id) { |
| 48 | case VERSAL_NET_SPP: |
| 49 | return "IPP"; |
| 50 | case VERSAL_NET_EMU: |
| 51 | return "EMU"; |
| 52 | case VERSAL_NET_SILICON: |
| 53 | return "Silicon"; |
| 54 | case VERSAL_NET_QEMU: |
| 55 | return "QEMU"; |
| 56 | default: |
| 57 | return "Unknown"; |
| 58 | } |
| 59 | } |
| 60 | |
| 61 | void board_detection(void) |
| 62 | { |
| 63 | uint32_t version; |
| 64 | |
| 65 | version = mmio_read_32(PMC_TAP_VERSION); |
| 66 | platform_id = FIELD_GET(PLATFORM_MASK, version); |
| 67 | platform_version = FIELD_GET(PLATFORM_VERSION_MASK, version); |
| 68 | |
Sai Pavan Boddu | 7524b22 | 2022-09-08 16:09:04 +0530 | [diff] [blame] | 69 | if (platform_id == VERSAL_NET_QEMU_COSIM) { |
| 70 | platform_id = VERSAL_NET_QEMU; |
| 71 | } |
| 72 | |
Michal Simek | 9179436 | 2022-08-31 16:45:14 +0200 | [diff] [blame] | 73 | if ((platform_id == VERSAL_NET_SPP) || |
| 74 | (platform_id == VERSAL_NET_EMU) || |
| 75 | (platform_id == VERSAL_NET_QEMU)) { |
| 76 | /* |
| 77 | * 9 is diff for |
| 78 | * 0 means 0.9 version |
| 79 | * 1 means 1.0 version |
| 80 | * 2 means 1.1 version |
| 81 | * etc, |
| 82 | */ |
| 83 | platform_version += 9U; |
| 84 | } |
| 85 | |
| 86 | /* Make sure that console is setup to see this message */ |
| 87 | VERBOSE("Platform id: %d version: %d.%d\n", platform_id, |
| 88 | platform_version / 10U, platform_version % 10U); |
| 89 | } |
| 90 | |
Prasad Kummari | e7e8f86 | 2023-10-04 10:20:30 +0530 | [diff] [blame] | 91 | uint32_t get_uart_clk(void) |
| 92 | { |
| 93 | uint32_t uart_clock; |
| 94 | |
| 95 | switch (platform_id) { |
| 96 | case VERSAL_NET_SPP: |
| 97 | uart_clock = 1000000; |
| 98 | break; |
| 99 | case VERSAL_NET_EMU: |
| 100 | uart_clock = 25000000; |
| 101 | break; |
| 102 | case VERSAL_NET_QEMU: |
| 103 | uart_clock = 25000000; |
| 104 | break; |
| 105 | case VERSAL_NET_SILICON: |
| 106 | uart_clock = 100000000; |
| 107 | break; |
| 108 | default: |
| 109 | panic(); |
| 110 | } |
| 111 | |
| 112 | return uart_clock; |
| 113 | } |
| 114 | |
Michal Simek | 9179436 | 2022-08-31 16:45:14 +0200 | [diff] [blame] | 115 | void versal_net_config_setup(void) |
| 116 | { |
Prasad Kummari | 2eb2279 | 2023-12-20 16:15:03 +0530 | [diff] [blame] | 117 | generic_delay_timer_init(); |
| 118 | |
| 119 | #if (TFA_NO_PM == 0) |
| 120 | /* Configure IPI data for versal_net */ |
| 121 | versal_net_ipi_config_table_init(); |
| 122 | #endif |
| 123 | } |
| 124 | |
| 125 | void syscnt_freq_config_setup(void) |
| 126 | { |
Michal Simek | 9179436 | 2022-08-31 16:45:14 +0200 | [diff] [blame] | 127 | uint32_t val; |
| 128 | uintptr_t crl_base, iou_scntrs_base, psx_base; |
| 129 | |
| 130 | crl_base = VERSAL_NET_CRL; |
Prasad Kummari | 8002802 | 2023-12-20 16:23:42 +0530 | [diff] [blame^] | 131 | iou_scntrs_base = IOU_SCNTRS_BASE; |
Michal Simek | 9179436 | 2022-08-31 16:45:14 +0200 | [diff] [blame] | 132 | psx_base = PSX_CRF; |
| 133 | |
| 134 | /* Reset for system timestamp generator in FPX */ |
| 135 | mmio_write_32(psx_base + PSX_CRF_RST_TIMESTAMP_OFFSET, 0); |
| 136 | |
| 137 | /* Global timer init - Program time stamp reference clk */ |
| 138 | val = mmio_read_32(crl_base + VERSAL_NET_CRL_TIMESTAMP_REF_CTRL_OFFSET); |
| 139 | val |= VERSAL_NET_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT; |
| 140 | mmio_write_32(crl_base + VERSAL_NET_CRL_TIMESTAMP_REF_CTRL_OFFSET, val); |
| 141 | |
| 142 | /* Clear reset of timestamp reg */ |
| 143 | mmio_write_32(crl_base + VERSAL_NET_CRL_RST_TIMESTAMP_OFFSET, 0); |
| 144 | |
| 145 | /* Program freq register in System counter and enable system counter. */ |
Prasad Kummari | 8002802 | 2023-12-20 16:23:42 +0530 | [diff] [blame^] | 146 | mmio_write_32(iou_scntrs_base + IOU_SCNTRS_BASE_FREQ_OFFSET, |
Michal Simek | 9179436 | 2022-08-31 16:45:14 +0200 | [diff] [blame] | 147 | cpu_clock); |
Prasad Kummari | 8002802 | 2023-12-20 16:23:42 +0530 | [diff] [blame^] | 148 | mmio_write_32(iou_scntrs_base + IOU_SCNTRS_COUNTER_CONTROL_REG_OFFSET, |
| 149 | IOU_SCNTRS_CONTROL_EN); |
Michal Simek | 9179436 | 2022-08-31 16:45:14 +0200 | [diff] [blame] | 150 | } |
| 151 | |
| 152 | uint32_t plat_get_syscnt_freq2(void) |
| 153 | { |
Prasad Kummari | 2eb2279 | 2023-12-20 16:15:03 +0530 | [diff] [blame] | 154 | uint32_t counter_freq = 0; |
| 155 | uint32_t ret = 0; |
| 156 | |
Prasad Kummari | 8002802 | 2023-12-20 16:23:42 +0530 | [diff] [blame^] | 157 | counter_freq = mmio_read_32(IOU_SCNTRS_BASE + |
| 158 | IOU_SCNTRS_BASE_FREQ_OFFSET); |
Prasad Kummari | 2eb2279 | 2023-12-20 16:15:03 +0530 | [diff] [blame] | 159 | if (counter_freq != 0U) { |
| 160 | ret = counter_freq; |
| 161 | } else { |
| 162 | INFO("Indicates counter frequency %dHz setting to %dHz\n", |
| 163 | counter_freq, cpu_clock); |
| 164 | ret = cpu_clock; |
| 165 | } |
| 166 | |
| 167 | return ret; |
Michal Simek | 9179436 | 2022-08-31 16:45:14 +0200 | [diff] [blame] | 168 | } |