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Tejas Patel354fe572018-12-14 00:55:37 -08001/*
Tanmay Shahff34daa2021-08-09 11:00:41 -07002 * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved.
Michal Simekd4ff2722023-04-20 08:01:03 +02003 * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
Tejas Patel354fe572018-12-14 00:55:37 -08004 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8/* Versal power management enums and defines */
9
10#ifndef PM_DEFS_H
11#define PM_DEFS_H
12
13#include "pm_node.h"
14
15/*********************************************************************
16 * Macro definitions
17 ********************************************************************/
18
Tejas Patel54d13192019-02-27 18:44:55 +053019/* State arguments of the self suspend */
20#define PM_STATE_CPU_IDLE 0x0U
Jay Buddhabhatti31488a32023-09-11 23:50:06 -070021#define PM_STATE_CPU_OFF 0x1U
Tejas Patel54d13192019-02-27 18:44:55 +053022#define PM_STATE_SUSPEND_TO_RAM 0xFU
23
24#define MAX_LATENCY (~0U)
25#define MAX_QOS 100U
26
Tejas Patel354fe572018-12-14 00:55:37 -080027/* Processor core device IDs */
28#define APU_DEVID(IDX) NODEID(XPM_NODECLASS_DEVICE, XPM_NODESUBCL_DEV_CORE, \
29 XPM_NODETYPE_DEV_CORE_APU, (IDX))
30
31#define XPM_DEVID_ACPU_0 APU_DEVID(XPM_NODEIDX_DEV_ACPU_0)
32#define XPM_DEVID_ACPU_1 APU_DEVID(XPM_NODEIDX_DEV_ACPU_1)
33
Jay Buddhabhattif2f84b32023-02-09 22:56:53 -080034#define PERIPH_DEVID(IDX) NODEID((uint32_t)XPM_NODECLASS_DEVICE, \
35 (uint32_t)XPM_NODESUBCL_DEV_PERIPH, \
36 (uint32_t)XPM_NODETYPE_DEV_PERIPH, (IDX))
Tejas Patelfcb7c162019-02-27 18:44:56 +053037
Abhyuday Godhasaraedc38ae2021-08-04 23:58:46 -070038#define PM_GET_CALLBACK_DATA 0xa01U
39#define PM_GET_TRUSTZONE_VERSION 0xa03U
Tanmay Shah0dde16c2021-12-14 04:53:40 -080040#define TF_A_PM_REGISTER_SGI 0xa04U
Ravi Patel22b0b492019-03-06 12:34:46 +053041
42/* PM API Versions */
43#define PM_API_BASE_VERSION 1U
Venkatesh Yadav Abbarapud90e47b2022-07-28 08:50:30 +053044#define PM_API_VERSION_2 2U
Rajan Vaja030620d2020-11-23 04:13:54 -080045
Jolly Shahed05a712019-03-22 05:33:39 +053046/* Loader API ids */
47#define PM_LOAD_PDI 0x701U
Venkatesh Yadav Abbarapu58b24d82022-07-12 09:19:03 +053048#define PM_LOAD_GET_HANDOFF_PARAMS 0x70BU
Jolly Shahed05a712019-03-22 05:33:39 +053049
Saeed Nowshadic5a1bda2019-12-08 23:35:35 -080050/* System shutdown macros */
51#define XPM_SHUTDOWN_TYPE_SHUTDOWN 0U
52#define XPM_SHUTDOWN_TYPE_RESET 1U
53#define XPM_SHUTDOWN_TYPE_SETSCOPE_ONLY 2U
54
55#define XPM_SHUTDOWN_SUBTYPE_RST_SUBSYSTEM 0U
56#define XPM_SHUTDOWN_SUBTYPE_RST_PS_ONLY 1U
57#define XPM_SHUTDOWN_SUBTYPE_RST_SYSTEM 2U
58
Tejas Patel354fe572018-12-14 00:55:37 -080059/*********************************************************************
60 * Enum definitions
61 ********************************************************************/
62
Prasad Kummari7d0623a2023-06-09 14:32:00 +053063/*
64 * ioctl id
65 */
Jay Buddhabhatti5b672d92023-03-23 05:02:50 -070066enum {
67 IOCTL_GET_RPU_OPER_MODE = 0,
68 IOCTL_SET_RPU_OPER_MODE = 1,
69 IOCTL_RPU_BOOT_ADDR_CONFIG = 2,
70 IOCTL_TCM_COMB_CONFIG = 3,
71 IOCTL_SET_TAPDELAY_BYPASS = 4,
Jay Buddhabhatti5b672d92023-03-23 05:02:50 -070072 IOCTL_SD_DLL_RESET = 6,
73 IOCTL_SET_SD_TAPDELAY = 7,
74 /* Ioctl for clock driver */
75 IOCTL_SET_PLL_FRAC_MODE = 8,
76 IOCTL_GET_PLL_FRAC_MODE = 9,
77 IOCTL_SET_PLL_FRAC_DATA = 10,
78 IOCTL_GET_PLL_FRAC_DATA = 11,
79 IOCTL_WRITE_GGS = 12,
80 IOCTL_READ_GGS = 13,
81 IOCTL_WRITE_PGGS = 14,
82 IOCTL_READ_PGGS = 15,
83 /* IOCTL for ULPI reset */
84 IOCTL_ULPI_RESET = 16,
85 /* Set healthy bit value */
86 IOCTL_SET_BOOT_HEALTH_STATUS = 17,
87 IOCTL_AFI = 18,
88 /* Probe counter read/write */
89 IOCTL_PROBE_COUNTER_READ = 19,
90 IOCTL_PROBE_COUNTER_WRITE = 20,
91 IOCTL_OSPI_MUX_SELECT = 21,
92 /* IOCTL for USB power request */
93 IOCTL_USB_SET_STATE = 22,
94 /* IOCTL to get last reset reason */
95 IOCTL_GET_LAST_RESET_REASON = 23,
96 /* AI engine NPI ISR clear */
97 IOCTL_AIE_ISR_CLEAR = 24,
98 /* Register SGI to TF-A */
99 IOCTL_SET_SGI = 25,
100};
101
Jay Buddhabhatti5b9f3912023-02-02 22:34:03 -0800102/**
Prasad Kummari7d0623a2023-06-09 14:32:00 +0530103 * enum pm_pll_param - enum represents the parameters for a phase-locked loop.
104 * @PM_PLL_PARAM_DIV2: Enable for divide by 2 function inside the PLL.
105 * @PM_PLL_PARAM_FBDIV: Feedback divisor integer portion for the PLL.
106 * @PM_PLL_PARAM_DATA: Feedback divisor fractional portion for the PLL.
107 * @PM_PLL_PARAM_PRE_SRC: Clock source for PLL input.
108 * @PM_PLL_PARAM_POST_SRC: Clock source for PLL Bypass mode.
109 * @PM_PLL_PARAM_LOCK_DLY: Lock circuit config settings for lock windowsize.
110 * @PM_PLL_PARAM_LOCK_CNT: Lock circuit counter setting.
111 * @PM_PLL_PARAM_LFHF: PLL loop filter high frequency capacitor control.
112 * @PM_PLL_PARAM_CP: PLL charge pump control.
113 * @PM_PLL_PARAM_RES: PLL loop filter resistor control.
114 * @PM_PLL_PARAM_MAX: Represents the maximum parameter value for the PLL
Jay Buddhabhatti5b9f3912023-02-02 22:34:03 -0800115 */
116enum pm_pll_param {
117 PM_PLL_PARAM_DIV2,
118 PM_PLL_PARAM_FBDIV,
119 PM_PLL_PARAM_DATA,
120 PM_PLL_PARAM_PRE_SRC,
121 PM_PLL_PARAM_POST_SRC,
122 PM_PLL_PARAM_LOCK_DLY,
123 PM_PLL_PARAM_LOCK_CNT,
124 PM_PLL_PARAM_LFHF,
125 PM_PLL_PARAM_CP,
126 PM_PLL_PARAM_RES,
127 PM_PLL_PARAM_MAX,
128};
129
130enum pm_api_id {
131 /* Miscellaneous API functions: */
132 PM_GET_API_VERSION = 1, /* Do not change or move */
133 PM_SET_CONFIGURATION,
134 PM_GET_NODE_STATUS,
135 PM_GET_OP_CHARACTERISTIC,
136 PM_REGISTER_NOTIFIER,
137 /* API for suspending of PUs: */
138 PM_REQ_SUSPEND,
139 PM_SELF_SUSPEND,
140 PM_FORCE_POWERDOWN,
141 PM_ABORT_SUSPEND,
142 PM_REQ_WAKEUP,
143 PM_SET_WAKEUP_SOURCE,
144 PM_SYSTEM_SHUTDOWN,
145 /* API for managing PM slaves: */
146 PM_REQ_NODE,
147 PM_RELEASE_NODE,
148 PM_SET_REQUIREMENT,
149 PM_SET_MAX_LATENCY,
150 /* Direct control API functions: */
151 PM_RESET_ASSERT,
152 PM_RESET_GET_STATUS,
153 PM_MMIO_WRITE,
154 PM_MMIO_READ,
155 PM_INIT_FINALIZE,
156 PM_FPGA_LOAD,
157 PM_FPGA_GET_STATUS,
158 PM_GET_CHIPID,
159 PM_SECURE_RSA_AES,
160 PM_SECURE_SHA,
161 PM_SECURE_RSA,
162 PM_PINCTRL_REQUEST,
163 PM_PINCTRL_RELEASE,
164 PM_PINCTRL_GET_FUNCTION,
165 PM_PINCTRL_SET_FUNCTION,
166 PM_PINCTRL_CONFIG_PARAM_GET,
167 PM_PINCTRL_CONFIG_PARAM_SET,
168 PM_IOCTL,
169 /* API to query information from firmware */
170 PM_QUERY_DATA,
171 /* Clock control API functions */
172 PM_CLOCK_ENABLE,
173 PM_CLOCK_DISABLE,
174 PM_CLOCK_GETSTATE,
175 PM_CLOCK_SETDIVIDER,
176 PM_CLOCK_GETDIVIDER,
Ronak Jaind5a3eff2023-08-02 01:28:10 -0700177 PM_CLOCK_SETPARENT = 43,
Jay Buddhabhatti5b9f3912023-02-02 22:34:03 -0800178 PM_CLOCK_GETPARENT,
179 PM_SECURE_IMAGE,
180 /* FPGA PL Readback */
181 PM_FPGA_READ,
182 PM_SECURE_AES,
183 /* PLL control API functions */
184 PM_PLL_SET_PARAMETER,
185 PM_PLL_GET_PARAMETER,
186 PM_PLL_SET_MODE,
187 PM_PLL_GET_MODE,
188 /* PM Register Access API */
189 PM_REGISTER_ACCESS,
190 PM_EFUSE_ACCESS,
191 PM_FPGA_GET_VERSION,
192 PM_FPGA_GET_FEATURE_LIST,
193 PM_FEATURE_CHECK = 63,
194 PM_API_MAX = 74
195};
196
Tejas Patelfe0e10a2019-12-08 23:29:44 -0800197enum pm_abort_reason {
198 ABORT_REASON_WKUP_EVENT = 100,
199 ABORT_REASON_PU_BUSY,
200 ABORT_REASON_NO_PWRDN,
201 ABORT_REASON_UNKNOWN,
202};
203
Saeed Nowshadi2294b422019-06-03 10:22:35 -0700204enum pm_opchar_type {
205 PM_OPCHAR_TYPE_POWER = 1,
206 PM_OPCHAR_TYPE_TEMP,
207 PM_OPCHAR_TYPE_LATENCY,
208};
209
Prasad Kummari7d0623a2023-06-09 14:32:00 +0530210/*
Tejas Patel41f3e0b2019-01-08 01:46:37 -0800211 * Subsystem IDs
212 */
213typedef enum {
214 XPM_SUBSYSID_PMC,
215 XPM_SUBSYSID_PSM,
216 XPM_SUBSYSID_APU,
217 XPM_SUBSYSID_RPU0_LOCK,
218 XPM_SUBSYSID_RPU0_0,
219 XPM_SUBSYSID_RPU0_1,
220 XPM_SUBSYSID_DDR0,
221 XPM_SUBSYSID_ME,
222 XPM_SUBSYSID_PL,
223 XPM_SUBSYSID_MAX,
224} XPm_SubsystemId;
225
Naman Trivedi Manojbhaic0dfba82023-03-07 12:41:11 +0530226/* TODO: move pm_ret_status from device specific location to common location */
Tejas Patel41f3e0b2019-01-08 01:46:37 -0800227/**
Prasad Kummari7d0623a2023-06-09 14:32:00 +0530228 * enum pm_ret_status - enum represents the return status codes for a PM
229 * operation.
230 * @PM_RET_SUCCESS: success.
231 * @PM_RET_ERROR_ARGS: illegal arguments provided (deprecated).
232 * @PM_RET_ERROR_NOTSUPPORTED: feature not supported (deprecated).
233 * @PM_RET_ERROR_NOFEATURE: feature is not available.
234 * @PM_RET_ERROR_INVALID_CRC: invalid crc in IPI communication.
235 * @PM_RET_ERROR_NOT_ENABLED: feature is not enabled.
236 * @PM_RET_ERROR_INTERNAL: internal error.
237 * @PM_RET_ERROR_CONFLICT: conflict.
238 * @PM_RET_ERROR_ACCESS: access rights violation.
239 * @PM_RET_ERROR_INVALID_NODE: invalid node.
240 * @PM_RET_ERROR_DOUBLE_REQ: duplicate request for same node.
241 * @PM_RET_ERROR_ABORT_SUSPEND: suspend procedure has been aborted.
242 * @PM_RET_ERROR_TIMEOUT: timeout in communication with PMU.
243 * @PM_RET_ERROR_NODE_USED: node is already in use.
244 * @PM_RET_ERROR_NO_FEATURE: indicates that the requested feature is not
245 * supported.
Tejas Patel354fe572018-12-14 00:55:37 -0800246 */
247enum pm_ret_status {
248 PM_RET_SUCCESS,
249 PM_RET_ERROR_ARGS = 1,
250 PM_RET_ERROR_NOTSUPPORTED = 4,
Ravi Patel22b0b492019-03-06 12:34:46 +0530251 PM_RET_ERROR_NOFEATURE = 19,
Naman Trivedi Manojbhaic0dfba82023-03-07 12:41:11 +0530252 PM_RET_ERROR_INVALID_CRC = 301,
Jay Buddhabhatti5b9f3912023-02-02 22:34:03 -0800253 PM_RET_ERROR_NOT_ENABLED = 29,
Tejas Patel354fe572018-12-14 00:55:37 -0800254 PM_RET_ERROR_INTERNAL = 2000,
255 PM_RET_ERROR_CONFLICT = 2001,
256 PM_RET_ERROR_ACCESS = 2002,
257 PM_RET_ERROR_INVALID_NODE = 2003,
258 PM_RET_ERROR_DOUBLE_REQ = 2004,
259 PM_RET_ERROR_ABORT_SUSPEND = 2005,
260 PM_RET_ERROR_TIMEOUT = 2006,
Jay Buddhabhatti5b9f3912023-02-02 22:34:03 -0800261 PM_RET_ERROR_NODE_USED = 2007,
262 PM_RET_ERROR_NO_FEATURE = 2008
Tejas Patel354fe572018-12-14 00:55:37 -0800263};
Rajan Vaja030620d2020-11-23 04:13:54 -0800264
Prasad Kummari7d0623a2023-06-09 14:32:00 +0530265/*
Rajan Vaja030620d2020-11-23 04:13:54 -0800266 * Qids
267 */
268enum pm_query_id {
269 XPM_QID_INVALID,
270 XPM_QID_CLOCK_GET_NAME,
271 XPM_QID_CLOCK_GET_TOPOLOGY,
272 XPM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS,
273 XPM_QID_CLOCK_GET_MUXSOURCES,
274 XPM_QID_CLOCK_GET_ATTRIBUTES,
275 XPM_QID_PINCTRL_GET_NUM_PINS,
276 XPM_QID_PINCTRL_GET_NUM_FUNCTIONS,
277 XPM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS,
278 XPM_QID_PINCTRL_GET_FUNCTION_NAME,
279 XPM_QID_PINCTRL_GET_FUNCTION_GROUPS,
280 XPM_QID_PINCTRL_GET_PIN_GROUPS,
281 XPM_QID_CLOCK_GET_NUM_CLOCKS,
282 XPM_QID_CLOCK_GET_MAX_DIVISOR,
283 XPM_QID_PLD_GET_PARENT,
284};
Tejas Patel354fe572018-12-14 00:55:37 -0800285#endif /* PM_DEFS_H */