| Etienne Carriere | 37f8cdc | 2017-11-05 22:56:26 +0100 | [diff] [blame] | 1 | /* |
| Boyan Karatotev | 2a6af38 | 2023-04-05 11:29:15 +0100 | [diff] [blame] | 2 | * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved. |
| Etienne Carriere | 37f8cdc | 2017-11-05 22:56:26 +0100 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
| 8 | #include <asm_macros.S> |
| 9 | #include <assert_macros.S> |
| 10 | #include <cortex_a5.h> |
| 11 | #include <cpu_macros.S> |
| 12 | |
| 13 | .macro assert_cache_enabled |
| 14 | #if ENABLE_ASSERTIONS |
| 15 | ldcopr r0, SCTLR |
| 16 | tst r0, #SCTLR_C_BIT |
| 17 | ASM_ASSERT(eq) |
| 18 | #endif |
| 19 | .endm |
| 20 | |
| 21 | func cortex_a5_disable_smp |
| 22 | ldcopr r0, ACTLR |
| 23 | bic r0, #CORTEX_A5_ACTLR_SMP_BIT |
| 24 | stcopr r0, ACTLR |
| 25 | isb |
| 26 | dsb sy |
| 27 | bx lr |
| 28 | endfunc cortex_a5_disable_smp |
| 29 | |
| 30 | func cortex_a5_enable_smp |
| 31 | ldcopr r0, ACTLR |
| 32 | orr r0, #CORTEX_A5_ACTLR_SMP_BIT |
| 33 | stcopr r0, ACTLR |
| 34 | isb |
| 35 | bx lr |
| 36 | endfunc cortex_a5_enable_smp |
| 37 | |
| 38 | func cortex_a5_reset_func |
| 39 | b cortex_a5_enable_smp |
| 40 | endfunc cortex_a5_reset_func |
| 41 | |
| 42 | func cortex_a5_core_pwr_dwn |
| 43 | push {r12, lr} |
| 44 | |
| 45 | assert_cache_enabled |
| 46 | |
| 47 | /* Flush L1 cache */ |
| 48 | mov r0, #DC_OP_CISW |
| 49 | bl dcsw_op_level1 |
| 50 | |
| 51 | /* Exit cluster coherency */ |
| 52 | pop {r12, lr} |
| 53 | b cortex_a5_disable_smp |
| 54 | endfunc cortex_a5_core_pwr_dwn |
| 55 | |
| 56 | func cortex_a5_cluster_pwr_dwn |
| 57 | push {r12, lr} |
| 58 | |
| 59 | assert_cache_enabled |
| 60 | |
| 61 | /* Flush L1 caches */ |
| 62 | mov r0, #DC_OP_CISW |
| 63 | bl dcsw_op_level1 |
| 64 | |
| 65 | bl plat_disable_acp |
| 66 | |
| 67 | /* Exit cluster coherency */ |
| 68 | pop {r12, lr} |
| 69 | b cortex_a5_disable_smp |
| 70 | endfunc cortex_a5_cluster_pwr_dwn |
| 71 | |
| Boyan Karatotev | 2a6af38 | 2023-04-05 11:29:15 +0100 | [diff] [blame] | 72 | errata_report_shim cortex_a5 |
| Soby Mathew | 0980dce | 2018-09-17 04:34:35 +0100 | [diff] [blame] | 73 | |
| Etienne Carriere | 37f8cdc | 2017-11-05 22:56:26 +0100 | [diff] [blame] | 74 | declare_cpu_ops cortex_a5, CORTEX_A5_MIDR, \ |
| 75 | cortex_a5_reset_func, \ |
| 76 | cortex_a5_core_pwr_dwn, \ |
| 77 | cortex_a5_cluster_pwr_dwn |