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Harry Liebelafd1ec72014-04-01 19:19:22 +01001/*
Dan Handley76076762015-03-19 19:26:52 +00002 * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
Harry Liebelafd1ec72014-04-01 19:19:22 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#ifndef __TZC400_H__
32#define __TZC400_H__
33
Harry Liebelafd1ec72014-04-01 19:19:22 +010034
35#define BUILD_CONFIG_OFF 0x000
36#define ACTION_OFF 0x004
37#define GATE_KEEPER_OFF 0x008
38#define SPECULATION_CTRL_OFF 0x00c
39#define INT_STATUS 0x010
40#define INT_CLEAR 0x014
41
42#define FAIL_ADDRESS_LOW_OFF 0x020
43#define FAIL_ADDRESS_HIGH_OFF 0x024
44#define FAIL_CONTROL_OFF 0x028
45#define FAIL_ID 0x02c
46
47#define REGION_BASE_LOW_OFF 0x100
48#define REGION_BASE_HIGH_OFF 0x104
49#define REGION_TOP_LOW_OFF 0x108
50#define REGION_TOP_HIGH_OFF 0x10c
51#define REGION_ATTRIBUTES_OFF 0x110
52#define REGION_ID_ACCESS_OFF 0x114
53#define REGION_NUM_OFF(region) (0x20 * region)
54
55/* ID Registers */
56#define PID0_OFF 0xfe0
57#define PID1_OFF 0xfe4
58#define PID2_OFF 0xfe8
59#define PID3_OFF 0xfec
60#define PID4_OFF 0xfd0
61#define PID5_OFF 0xfd4
62#define PID6_OFF 0xfd8
63#define PID7_OFF 0xfdc
64#define CID0_OFF 0xff0
65#define CID1_OFF 0xff4
66#define CID2_OFF 0xff8
67#define CID3_OFF 0xffc
68
69#define BUILD_CONFIG_NF_SHIFT 24
70#define BUILD_CONFIG_NF_MASK 0x3
71#define BUILD_CONFIG_AW_SHIFT 8
72#define BUILD_CONFIG_AW_MASK 0x3f
73#define BUILD_CONFIG_NR_SHIFT 0
74#define BUILD_CONFIG_NR_MASK 0x1f
75
76/* Not describing the case where regions 1 to 8 overlap */
77#define ACTION_RV_SHIFT 0
78#define ACTION_RV_MASK 0x3
79#define ACTION_RV_LOWOK 0x0
80#define ACTION_RV_LOWERR 0x1
81#define ACTION_RV_HIGHOK 0x2
82#define ACTION_RV_HIGHERR 0x3
83
84/*
85 * Number of gate keepers is implementation defined. But we know the max for
86 * this device is 4. Get implementation details from BUILD_CONFIG.
87 */
88#define GATE_KEEPER_OS_SHIFT 16
89#define GATE_KEEPER_OS_MASK 0xf
90#define GATE_KEEPER_OR_SHIFT 0
91#define GATE_KEEPER_OR_MASK 0xf
Juan Castillof558cac2014-06-05 09:45:36 +010092#define GATE_KEEPER_FILTER_MASK 0x1
Harry Liebelafd1ec72014-04-01 19:19:22 +010093
94/* Speculation is enabled by default. */
95#define SPECULATION_CTRL_WRITE_DISABLE (1 << 1)
96#define SPECULATION_CTRL_READ_DISABLE (1 << 0)
97
98/* Max number of filters allowed is 4. */
99#define INT_STATUS_OVERLAP_SHIFT 16
100#define INT_STATUS_OVERLAP_MASK 0xf
101#define INT_STATUS_OVERRUN_SHIFT 8
102#define INT_STATUS_OVERRUN_MASK 0xf
103#define INT_STATUS_STATUS_SHIFT 0
104#define INT_STATUS_STATUS_MASK 0xf
105
106#define INT_CLEAR_CLEAR_SHIFT 0
107#define INT_CLEAR_CLEAR_MASK 0xf
108
109#define FAIL_CONTROL_DIR_SHIFT (1 << 24)
110#define FAIL_CONTROL_DIR_READ 0x0
111#define FAIL_CONTROL_DIR_WRITE 0x1
112#define FAIL_CONTROL_NS_SHIFT (1 << 21)
113#define FAIL_CONTROL_NS_SECURE 0x0
114#define FAIL_CONTROL_NS_NONSECURE 0x1
115#define FAIL_CONTROL_PRIV_SHIFT (1 << 20)
116#define FAIL_CONTROL_PRIV_PRIV 0x0
117#define FAIL_CONTROL_PRIV_UNPRIV 0x1
118
119/*
120 * FAIL_ID_ID_MASK depends on AID_WIDTH which is platform specific.
121 * Platform should provide the value on initialisation.
122 */
123#define FAIL_ID_VNET_SHIFT 24
124#define FAIL_ID_VNET_MASK 0xf
125#define FAIL_ID_ID_SHIFT 0
126
127/* Used along with 'tzc_region_attributes_t' below */
Juan Castillo921b8772014-09-05 17:29:38 +0100128#define REG_ATTR_SEC_SHIFT 30
129#define REG_ATTR_F_EN_SHIFT 0
130#define REG_ATTR_F_EN_MASK 0xf
131#define REG_ATTR_FILTER_BIT(x) ((1 << x) << REG_ATTR_F_EN_SHIFT)
132#define REG_ATTR_FILTER_BIT_ALL (REG_ATTR_F_EN_MASK << \
133 REG_ATTR_F_EN_SHIFT)
Harry Liebelafd1ec72014-04-01 19:19:22 +0100134
135#define REGION_ID_ACCESS_NSAID_WR_EN_SHIFT 16
136#define REGION_ID_ACCESS_NSAID_RD_EN_SHIFT 0
137#define REGION_ID_ACCESS_NSAID_ID_MASK 0xf
138
139
140/* Macros for setting Region ID access permissions based on NSAID */
141#define TZC_REGION_ACCESS_RD(id) \
142 ((1 << (id & REGION_ID_ACCESS_NSAID_ID_MASK)) << \
143 REGION_ID_ACCESS_NSAID_RD_EN_SHIFT)
144#define TZC_REGION_ACCESS_WR(id) \
145 ((1 << (id & REGION_ID_ACCESS_NSAID_ID_MASK)) << \
146 REGION_ID_ACCESS_NSAID_WR_EN_SHIFT)
147#define TZC_REGION_ACCESS_RDWR(id) \
148 (TZC_REGION_ACCESS_RD(id) | TZC_REGION_ACCESS_WR(id))
149
Harry Liebelafd1ec72014-04-01 19:19:22 +0100150#define TZC400_COMPONENT_ID 0xb105f00d
151
Dan Handley76076762015-03-19 19:26:52 +0000152
153#ifndef __ASSEMBLY__
154
155#include <stdint.h>
156
Harry Liebelafd1ec72014-04-01 19:19:22 +0100157/*******************************************************************************
158 * Function & variable prototypes
159 ******************************************************************************/
160
161/*
162 * What type of action is expected when an access violation occurs.
163 * The memory requested is zeroed. But we can also raise and event to
164 * let the system know it happened.
165 * We can raise an interrupt(INT) and/or cause an exception(ERR).
166 * TZC_ACTION_NONE - No interrupt, no Exception
167 * TZC_ACTION_ERR - No interrupt, raise exception -> sync external
168 * data abort
169 * TZC_ACTION_INT - Raise interrupt, no exception
170 * TZC_ACTION_ERR_INT - Raise interrupt, raise exception -> sync
171 * external data abort
172 */
Dan Handleye2712bc2014-04-10 15:37:22 +0100173typedef enum {
Harry Liebelafd1ec72014-04-01 19:19:22 +0100174 TZC_ACTION_NONE = 0,
175 TZC_ACTION_ERR = 1,
176 TZC_ACTION_INT = 2,
177 TZC_ACTION_ERR_INT = (TZC_ACTION_ERR | TZC_ACTION_INT)
Dan Handleye2712bc2014-04-10 15:37:22 +0100178} tzc_action_t;
Harry Liebelafd1ec72014-04-01 19:19:22 +0100179
180/*
181 * Controls secure access to a region. If not enabled secure access is not
182 * allowed to region.
183 */
Dan Handleye2712bc2014-04-10 15:37:22 +0100184typedef enum {
Harry Liebelafd1ec72014-04-01 19:19:22 +0100185 TZC_REGION_S_NONE = 0,
186 TZC_REGION_S_RD = 1,
187 TZC_REGION_S_WR = 2,
188 TZC_REGION_S_RDWR = (TZC_REGION_S_RD | TZC_REGION_S_WR)
Dan Handleye2712bc2014-04-10 15:37:22 +0100189} tzc_region_attributes_t;
Harry Liebelafd1ec72014-04-01 19:19:22 +0100190
Harry Liebelafd1ec72014-04-01 19:19:22 +0100191
Juan Castillo7f1f0622014-09-09 09:49:23 +0100192void tzc_init(uintptr_t base);
Dan Handley76076762015-03-19 19:26:52 +0000193void tzc_configure_region0(tzc_region_attributes_t sec_attr,
194 uint32_t ns_device_access);
Dan Handley53c843a2014-08-04 19:53:05 +0100195void tzc_configure_region(uint32_t filters,
196 uint8_t region,
197 uint64_t region_base,
198 uint64_t region_top,
199 tzc_region_attributes_t sec_attr,
200 uint32_t ns_device_access);
201void tzc_enable_filters(void);
202void tzc_disable_filters(void);
203void tzc_set_action(tzc_action_t action);
Harry Liebelafd1ec72014-04-01 19:19:22 +0100204
Dan Handley76076762015-03-19 19:26:52 +0000205#endif /* __ASSEMBLY__ */
Harry Liebelafd1ec72014-04-01 19:19:22 +0100206
207#endif /* __TZC400__ */