Robert Marko | 9c523ec | 2021-10-11 16:25:49 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2021 Sartura Ltd. |
| 3 | * Copyright (C) 2021 Globalscale technologies, Inc. |
| 4 | * Copyright (C) 2021 Marvell International Ltd. |
| 5 | * |
| 6 | * SPDX-License-Identifier: BSD-3-Clause |
| 7 | * https://spdx.org/licenses |
| 8 | */ |
| 9 | |
| 10 | #include <armada_common.h> |
| 11 | |
| 12 | /* |
| 13 | * If bootrom is currently at BLE there's no need to include the memory |
| 14 | * maps structure at this point |
| 15 | */ |
| 16 | #include <mvebu_def.h> |
| 17 | #ifndef IMAGE_BLE |
| 18 | |
| 19 | /***************************************************************************** |
| 20 | * AMB Configuration |
| 21 | ***************************************************************************** |
| 22 | */ |
| 23 | struct addr_map_win amb_memory_map[] = { |
| 24 | /* CP0 SPI1 CS0 Direct Mode access */ |
| 25 | {0xf900, 0x1000000, AMB_SPI1_CS0_ID}, |
| 26 | }; |
| 27 | |
| 28 | int marvell_get_amb_memory_map(struct addr_map_win **win, |
| 29 | uint32_t *size, uintptr_t base) |
| 30 | { |
| 31 | *win = amb_memory_map; |
| 32 | if (*win == NULL) |
| 33 | *size = 0; |
| 34 | else |
| 35 | *size = ARRAY_SIZE(amb_memory_map); |
| 36 | |
| 37 | return 0; |
| 38 | } |
| 39 | #endif |
| 40 | |
| 41 | /***************************************************************************** |
| 42 | * IO_WIN Configuration |
| 43 | ***************************************************************************** |
| 44 | */ |
| 45 | struct addr_map_win io_win_memory_map[] = { |
| 46 | #ifndef IMAGE_BLE |
| 47 | /* MCI 0 indirect window */ |
| 48 | {MVEBU_MCI_REG_BASE_REMAP(0), 0x100000, MCI_0_TID}, |
| 49 | /* MCI 1 indirect window */ |
| 50 | {MVEBU_MCI_REG_BASE_REMAP(1), 0x100000, MCI_1_TID}, |
| 51 | #endif |
| 52 | }; |
| 53 | |
| 54 | uint32_t marvell_get_io_win_gcr_target(int ap_index) |
| 55 | { |
| 56 | return PIDI_TID; |
| 57 | } |
| 58 | |
| 59 | int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, |
| 60 | uint32_t *size) |
| 61 | { |
| 62 | *win = io_win_memory_map; |
| 63 | if (*win == NULL) |
| 64 | *size = 0; |
| 65 | else |
| 66 | *size = ARRAY_SIZE(io_win_memory_map); |
| 67 | |
| 68 | return 0; |
| 69 | } |
| 70 | |
| 71 | #ifndef IMAGE_BLE |
| 72 | /***************************************************************************** |
| 73 | * IOB Configuration |
| 74 | ***************************************************************************** |
| 75 | */ |
| 76 | struct addr_map_win iob_memory_map[] = { |
| 77 | /* PEX1_X1 window */ |
| 78 | {0x00000000f7000000, 0x1000000, PEX1_TID}, |
| 79 | /* PEX2_X1 window */ |
| 80 | {0x00000000f8000000, 0x1000000, PEX2_TID}, |
| 81 | {0x00000000c0000000, 0x30000000, PEX2_TID}, |
| 82 | {0x0000000800000000, 0x100000000, PEX2_TID}, |
| 83 | /* PEX0_X4 window */ |
| 84 | {0x00000000f6000000, 0x1000000, PEX0_TID}, |
| 85 | /* SPI1_CS0 (RUNIT) window */ |
| 86 | {0x00000000f9000000, 0x1000000, RUNIT_TID}, |
| 87 | }; |
| 88 | |
| 89 | int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size, |
| 90 | uintptr_t base) |
| 91 | { |
| 92 | *win = iob_memory_map; |
| 93 | *size = ARRAY_SIZE(iob_memory_map); |
| 94 | |
| 95 | return 0; |
| 96 | } |
| 97 | #endif |
| 98 | |
| 99 | /***************************************************************************** |
| 100 | * CCU Configuration |
| 101 | ***************************************************************************** |
| 102 | */ |
| 103 | struct addr_map_win ccu_memory_map[] = { /* IO window */ |
| 104 | #ifdef IMAGE_BLE |
| 105 | {0x00000000f2000000, 0x4000000, IO_0_TID}, /* IO window */ |
| 106 | #else |
| 107 | #if LLC_SRAM |
| 108 | /* This entry is prepared for OP-TEE OS that enables the LLC SRAM |
| 109 | * and changes the window target to SRAM_TID. |
| 110 | */ |
| 111 | {PLAT_MARVELL_LLC_SRAM_BASE, PLAT_MARVELL_LLC_SRAM_SIZE, DRAM_0_TID}, |
| 112 | #endif |
| 113 | {0x00000000f2000000, 0xe000000, IO_0_TID}, |
| 114 | {0x00000000c0000000, 0x30000000, IO_0_TID}, /* IO window */ |
| 115 | {0x0000000800000000, 0x100000000, IO_0_TID}, /* IO window */ |
| 116 | #endif |
| 117 | }; |
| 118 | |
| 119 | uint32_t marvell_get_ccu_gcr_target(int ap) |
| 120 | { |
| 121 | return DRAM_0_TID; |
| 122 | } |
| 123 | |
| 124 | int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win, |
| 125 | uint32_t *size) |
| 126 | { |
| 127 | *win = ccu_memory_map; |
| 128 | *size = ARRAY_SIZE(ccu_memory_map); |
| 129 | |
| 130 | return 0; |
| 131 | } |
| 132 | |
| 133 | #ifdef IMAGE_BLE |
| 134 | /***************************************************************************** |
| 135 | * SKIP IMAGE Configuration |
| 136 | ***************************************************************************** |
| 137 | */ |
| 138 | #if PLAT_RECOVERY_IMAGE_ENABLE |
| 139 | void *plat_marvell_get_skip_image_data(void) |
| 140 | { |
| 141 | /* No recovery button on a70x0_mochabin board */ |
| 142 | return NULL; |
| 143 | } |
| 144 | #endif |
| 145 | #endif |