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tony.xie54973e72017-04-24 16:18:10 +08001/*
Lin Huang30e43392017-05-04 16:02:45 +08002 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
tony.xie54973e72017-04-24 16:18:10 +08003 *
dp-armd91aaae2017-05-10 15:16:15 +01004 * SPDX-License-Identifier: BSD-3-Clause
tony.xie54973e72017-04-24 16:18:10 +08005 */
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +00006#ifndef ROCKCHIP_PLAT_LD_S
7#define ROCKCHIP_PLAT_LD_S
tony.xie54973e72017-04-24 16:18:10 +08008
9MEMORY {
Lin Huang30e43392017-05-04 16:02:45 +080010 PMUSRAM (rwx): ORIGIN = PMUSRAM_BASE, LENGTH = PMUSRAM_RSIZE
tony.xie54973e72017-04-24 16:18:10 +080011}
12
13SECTIONS
14{
Lin Huang30e43392017-05-04 16:02:45 +080015 . = PMUSRAM_BASE;
tony.xie54973e72017-04-24 16:18:10 +080016
17 /*
Lin Huang30e43392017-05-04 16:02:45 +080018 * pmu_cpuson_entrypoint request address
19 * align 64K when resume, so put it in the
20 * start of pmusram
tony.xie54973e72017-04-24 16:18:10 +080021 */
Lin Huang30e43392017-05-04 16:02:45 +080022 .text_pmusram : {
23 ASSERT(. == ALIGN(64 * 1024),
24 ".pmusram.entry request 64K aligned.");
25 *(.pmusram.entry)
26 __bl31_pmusram_text_start = .;
27 *(.pmusram.text)
28 *(.pmusram.rodata)
29 __bl31_pmusram_text_end = .;
30 __bl31_pmusram_data_start = .;
31 *(.pmusram.data)
32 __bl31_pmusram_data_end = .;
tony.xie54973e72017-04-24 16:18:10 +080033
Lin Huang30e43392017-05-04 16:02:45 +080034 } >PMUSRAM
tony.xie54973e72017-04-24 16:18:10 +080035}
36
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +000037#endif /* ROCKCHIP_PLAT_LD_S */