Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 1 | /* |
Antonio Nino Diaz | 4b32e62 | 2018-08-16 16:52:57 +0100 | [diff] [blame] | 2 | * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. |
Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #include <assert.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 8 | #include <string.h> |
| 9 | |
Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 10 | #include <platform_def.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 11 | |
| 12 | #include <common/bl_common.h> |
| 13 | #include <common/debug.h> |
| 14 | |
Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 15 | #include <smmu.h> |
Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 16 | #include <tegra_private.h> |
Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 17 | |
Antonio Nino Diaz | 4b32e62 | 2018-08-16 16:52:57 +0100 | [diff] [blame] | 18 | extern void memcpy16(void *dest, const void *src, unsigned int length); |
| 19 | |
Pritesh Raithatha | 0de6e53 | 2017-01-24 13:49:46 +0530 | [diff] [blame] | 20 | /* SMMU IDs currently supported by the driver */ |
| 21 | enum { |
| 22 | TEGRA_SMMU0, |
| 23 | TEGRA_SMMU1, |
| 24 | TEGRA_SMMU2 |
| 25 | }; |
| 26 | |
| 27 | static uint32_t tegra_smmu_read_32(uint32_t smmu_id, uint32_t off) |
| 28 | { |
| 29 | #if defined(TEGRA_SMMU0_BASE) |
| 30 | if (smmu_id == TEGRA_SMMU0) |
| 31 | return mmio_read_32(TEGRA_SMMU0_BASE + off); |
| 32 | #endif |
| 33 | |
| 34 | #if defined(TEGRA_SMMU1_BASE) |
| 35 | if (smmu_id == TEGRA_SMMU1) |
| 36 | return mmio_read_32(TEGRA_SMMU1_BASE + off); |
| 37 | #endif |
| 38 | |
| 39 | #if defined(TEGRA_SMMU2_BASE) |
| 40 | if (smmu_id == TEGRA_SMMU2) |
| 41 | return mmio_read_32(TEGRA_SMMU2_BASE + off); |
| 42 | #endif |
| 43 | |
| 44 | return 0; |
| 45 | } |
| 46 | |
| 47 | static void tegra_smmu_write_32(uint32_t smmu_id, |
| 48 | uint32_t off, uint32_t val) |
| 49 | { |
| 50 | #if defined(TEGRA_SMMU0_BASE) |
| 51 | if (smmu_id == TEGRA_SMMU0) |
| 52 | mmio_write_32(TEGRA_SMMU0_BASE + off, val); |
| 53 | #endif |
| 54 | |
| 55 | #if defined(TEGRA_SMMU1_BASE) |
| 56 | if (smmu_id == TEGRA_SMMU1) |
| 57 | mmio_write_32(TEGRA_SMMU1_BASE + off, val); |
| 58 | #endif |
| 59 | |
| 60 | #if defined(TEGRA_SMMU2_BASE) |
| 61 | if (smmu_id == TEGRA_SMMU2) |
| 62 | mmio_write_32(TEGRA_SMMU2_BASE + off, val); |
| 63 | #endif |
| 64 | } |
| 65 | |
Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 66 | /* |
Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 67 | * Save SMMU settings before "System Suspend" to TZDRAM |
Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 68 | */ |
Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 69 | void tegra_smmu_save_context(uint64_t smmu_ctx_addr) |
Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 70 | { |
Varun Wadekar | 27155fc | 2017-04-20 18:56:09 -0700 | [diff] [blame] | 71 | uint32_t i, num_entries = 0; |
Pritesh Raithatha | c88654f | 2017-01-02 20:11:32 +0530 | [diff] [blame] | 72 | smmu_regs_t *smmu_ctx_regs; |
Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 73 | plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); |
| 74 | uint64_t tzdram_base = params_from_bl2->tzdram_base; |
| 75 | uint64_t tzdram_end = tzdram_base + params_from_bl2->tzdram_size; |
Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 76 | uint32_t reg_id1, pgshift, cb_size; |
| 77 | |
| 78 | /* sanity check SMMU settings c*/ |
Pritesh Raithatha | 0de6e53 | 2017-01-24 13:49:46 +0530 | [diff] [blame] | 79 | reg_id1 = mmio_read_32((TEGRA_SMMU0_BASE + SMMU_GNSR0_IDR1)); |
Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 80 | pgshift = (reg_id1 & ID1_PAGESIZE) ? 16 : 12; |
| 81 | cb_size = (2 << pgshift) * \ |
| 82 | (1 << (((reg_id1 >> ID1_NUMPAGENDXB_SHIFT) & ID1_NUMPAGENDXB_MASK) + 1)); |
| 83 | |
| 84 | assert(!((pgshift != PGSHIFT) || (cb_size != CB_SIZE))); |
Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 85 | assert((smmu_ctx_addr >= tzdram_base) && (smmu_ctx_addr <= tzdram_end)); |
| 86 | |
Pritesh Raithatha | c88654f | 2017-01-02 20:11:32 +0530 | [diff] [blame] | 87 | /* get SMMU context table */ |
| 88 | smmu_ctx_regs = plat_get_smmu_ctx(); |
| 89 | assert(smmu_ctx_regs); |
Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 90 | |
Varun Wadekar | 27155fc | 2017-04-20 18:56:09 -0700 | [diff] [blame] | 91 | /* |
| 92 | * smmu_ctx_regs[0].val contains the size of the context table minus |
| 93 | * the last entry. Sanity check the table size before we start with |
| 94 | * the context save operation. |
| 95 | */ |
| 96 | while (smmu_ctx_regs[num_entries].val != 0xFFFFFFFFU) { |
| 97 | num_entries++; |
| 98 | } |
| 99 | |
| 100 | /* panic if the sizes do not match */ |
| 101 | if (num_entries != smmu_ctx_regs[0].val) |
| 102 | panic(); |
| 103 | |
Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 104 | /* save SMMU register values */ |
Varun Wadekar | 27155fc | 2017-04-20 18:56:09 -0700 | [diff] [blame] | 105 | for (i = 1; i < num_entries; i++) |
Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 106 | smmu_ctx_regs[i].val = mmio_read_32(smmu_ctx_regs[i].reg); |
| 107 | |
Varun Wadekar | 27155fc | 2017-04-20 18:56:09 -0700 | [diff] [blame] | 108 | /* increment by 1 to take care of the last entry */ |
| 109 | num_entries++; |
| 110 | |
Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 111 | /* Save SMMU config settings */ |
| 112 | memcpy16((void *)(uintptr_t)smmu_ctx_addr, (void *)smmu_ctx_regs, |
Varun Wadekar | 27155fc | 2017-04-20 18:56:09 -0700 | [diff] [blame] | 113 | (sizeof(smmu_regs_t) * num_entries)); |
Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 114 | |
Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 115 | /* save the SMMU table address */ |
| 116 | mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV11_LO, |
Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 117 | (uint32_t)smmu_ctx_addr); |
Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 118 | mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV11_HI, |
Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 119 | (uint32_t)(smmu_ctx_addr >> 32)); |
Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 120 | } |
| 121 | |
Varun Wadekar | ea709c3 | 2016-04-20 17:14:15 -0700 | [diff] [blame] | 122 | #define SMMU_NUM_CONTEXTS 64 |
| 123 | #define SMMU_CONTEXT_BANK_MAX_IDX 64 |
| 124 | |
Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 125 | /* |
| 126 | * Init SMMU during boot or "System Suspend" exit |
| 127 | */ |
| 128 | void tegra_smmu_init(void) |
| 129 | { |
Pritesh Raithatha | 0de6e53 | 2017-01-24 13:49:46 +0530 | [diff] [blame] | 130 | uint32_t val, cb_idx, smmu_id, ctx_base; |
Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 131 | |
Pritesh Raithatha | 0de6e53 | 2017-01-24 13:49:46 +0530 | [diff] [blame] | 132 | for (smmu_id = 0; smmu_id < NUM_SMMU_DEVICES; smmu_id++) { |
| 133 | /* Program the SMMU pagesize and reset CACHE_LOCK bit */ |
| 134 | val = tegra_smmu_read_32(smmu_id, SMMU_GSR0_SECURE_ACR); |
| 135 | val |= SMMU_GSR0_PGSIZE_64K; |
| 136 | val &= ~SMMU_ACR_CACHE_LOCK_ENABLE_BIT; |
| 137 | tegra_smmu_write_32(smmu_id, SMMU_GSR0_SECURE_ACR, val); |
Varun Wadekar | ea709c3 | 2016-04-20 17:14:15 -0700 | [diff] [blame] | 138 | |
Pritesh Raithatha | 0de6e53 | 2017-01-24 13:49:46 +0530 | [diff] [blame] | 139 | /* reset CACHE LOCK bit for NS Aux. Config. Register */ |
| 140 | val = tegra_smmu_read_32(smmu_id, SMMU_GNSR_ACR); |
| 141 | val &= ~SMMU_ACR_CACHE_LOCK_ENABLE_BIT; |
| 142 | tegra_smmu_write_32(smmu_id, SMMU_GNSR_ACR, val); |
Varun Wadekar | ea709c3 | 2016-04-20 17:14:15 -0700 | [diff] [blame] | 143 | |
Pritesh Raithatha | 0de6e53 | 2017-01-24 13:49:46 +0530 | [diff] [blame] | 144 | /* disable TCU prefetch for all contexts */ |
| 145 | ctx_base = (SMMU_GSR0_PGSIZE_64K * SMMU_NUM_CONTEXTS) |
| 146 | + SMMU_CBn_ACTLR; |
| 147 | for (cb_idx = 0; cb_idx < SMMU_CONTEXT_BANK_MAX_IDX; cb_idx++) { |
| 148 | val = tegra_smmu_read_32(smmu_id, |
| 149 | ctx_base + (SMMU_GSR0_PGSIZE_64K * cb_idx)); |
| 150 | val &= ~SMMU_CBn_ACTLR_CPRE_BIT; |
| 151 | tegra_smmu_write_32(smmu_id, ctx_base + |
| 152 | (SMMU_GSR0_PGSIZE_64K * cb_idx), val); |
| 153 | } |
Varun Wadekar | ea709c3 | 2016-04-20 17:14:15 -0700 | [diff] [blame] | 154 | |
Pritesh Raithatha | 0de6e53 | 2017-01-24 13:49:46 +0530 | [diff] [blame] | 155 | /* set CACHE LOCK bit for NS Aux. Config. Register */ |
| 156 | val = tegra_smmu_read_32(smmu_id, SMMU_GNSR_ACR); |
| 157 | val |= SMMU_ACR_CACHE_LOCK_ENABLE_BIT; |
| 158 | tegra_smmu_write_32(smmu_id, SMMU_GNSR_ACR, val); |
Varun Wadekar | ea709c3 | 2016-04-20 17:14:15 -0700 | [diff] [blame] | 159 | |
Pritesh Raithatha | 0de6e53 | 2017-01-24 13:49:46 +0530 | [diff] [blame] | 160 | /* set CACHE LOCK bit for S Aux. Config. Register */ |
| 161 | val = tegra_smmu_read_32(smmu_id, SMMU_GSR0_SECURE_ACR); |
| 162 | val |= SMMU_ACR_CACHE_LOCK_ENABLE_BIT; |
| 163 | tegra_smmu_write_32(smmu_id, SMMU_GSR0_SECURE_ACR, val); |
| 164 | } |
Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 165 | } |