blob: bda406bba399cd36a363b8568d2a15285caad8c4 [file] [log] [blame]
Vijayenthiran Subramaniamad3fc762019-09-16 17:05:08 +05301/*
2 * Copyright (c) 2019, ARM Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef GIC600_MULTICHIP_H
8#define GIC600_MULTICHIP_H
9
10#include <stdint.h>
11
12/*
13 * GIC-600 microarchitecture supports coherent multichip environments containing
14 * up to 16 chips.
15 */
16#define GIC600_MAX_MULTICHIP 16
17
18/* SPI IDs array consist of min and max ids */
19#define GIC600_SPI_IDS_SIZE 2
20
21/*******************************************************************************
22 * GIC-600 multichip data structure describes platform specific attributes
23 * related to GIC-600 multichip. Platform port is expected to define these
24 * attributes to initialize the multichip related registers and create
25 * successful connections between the GIC-600s in a multichip system.
26 *
27 * The 'rt_owner_base' field contains the base address of the GIC Distributor
28 * which owns the routing table.
29 *
30 * The 'rt_owner' field contains the chip number which owns the routing table.
31 * Chip number or chip_id starts from 0.
32 *
33 * The 'chip_count' field contains the total number of chips in a multichip
34 * system. This should match the number of entries in 'chip_addrs' and 'spi_ids'
35 * fields.
36 *
37 * The 'chip_addrs' field contains array of chip addresses. These addresses are
38 * implementation specific values.
39 *
40 * The 'spi_ids' field contains array of minimum and maximum SPI interrupt ids
41 * that each chip owns. Note that SPI interrupt ids can range from 32 to 960 and
42 * it should be group of 32 (i.e., SPI minimum and (SPI maximum + 1) should be
43 * a multiple of 32). If a chip doesn't own any SPI interrupts a value of {0, 0}
44 * should be passed.
45 ******************************************************************************/
46struct gic600_multichip_data {
47 uintptr_t rt_owner_base;
48 unsigned int rt_owner;
49 unsigned int chip_count;
50 uint64_t chip_addrs[GIC600_MAX_MULTICHIP];
51 unsigned int spi_ids[GIC600_MAX_MULTICHIP][GIC600_SPI_IDS_SIZE];
52};
53
54void gic600_multichip_init(struct gic600_multichip_data *multichip_data);
55#endif /* GIC600_MULTICHIP_H */