Samuel Holland | b856664 | 2017-08-12 04:07:39 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
Samuel Holland | b856664 | 2017-08-12 04:07:39 -0500 | [diff] [blame] | 7 | #include <assert.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 8 | |
Andre Przywara | ea5fa47 | 2018-09-16 02:08:06 +0100 | [diff] [blame] | 9 | #include <libfdt.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 10 | |
Samuel Holland | b856664 | 2017-08-12 04:07:39 -0500 | [diff] [blame] | 11 | #include <platform_def.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 12 | |
| 13 | #include <arch.h> |
Samuel Holland | c629daf | 2019-02-17 15:33:33 -0600 | [diff] [blame] | 14 | #include <arch_helpers.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 15 | #include <common/debug.h> |
| 16 | #include <drivers/arm/gicv2.h> |
| 17 | #include <drivers/console.h> |
| 18 | #include <drivers/generic_delay_timer.h> |
| 19 | #include <drivers/ti/uart/uart_16550.h> |
| 20 | #include <lib/mmio.h> |
| 21 | #include <plat/common/platform.h> |
| 22 | |
Samuel Holland | b856664 | 2017-08-12 04:07:39 -0500 | [diff] [blame] | 23 | #include <sunxi_def.h> |
| 24 | #include <sunxi_mmap.h> |
Andre Przywara | 456208a | 2018-10-14 12:02:02 +0100 | [diff] [blame] | 25 | #include <sunxi_private.h> |
Samuel Holland | b856664 | 2017-08-12 04:07:39 -0500 | [diff] [blame] | 26 | |
Samuel Holland | b856664 | 2017-08-12 04:07:39 -0500 | [diff] [blame] | 27 | |
Amit Singh Tomar | 2f37224 | 2018-06-20 00:44:50 +0530 | [diff] [blame] | 28 | static entry_point_info_t bl32_image_ep_info; |
Samuel Holland | b856664 | 2017-08-12 04:07:39 -0500 | [diff] [blame] | 29 | static entry_point_info_t bl33_image_ep_info; |
| 30 | |
Andre Przywara | 98b5a11 | 2020-01-25 00:58:35 +0000 | [diff] [blame] | 31 | static console_t console; |
Samuel Holland | b856664 | 2017-08-12 04:07:39 -0500 | [diff] [blame] | 32 | |
| 33 | static const gicv2_driver_data_t sunxi_gic_data = { |
| 34 | .gicd_base = SUNXI_GICD_BASE, |
| 35 | .gicc_base = SUNXI_GICC_BASE, |
| 36 | }; |
| 37 | |
Andre Przywara | ea5fa47 | 2018-09-16 02:08:06 +0100 | [diff] [blame] | 38 | /* |
| 39 | * Try to find a DTB loaded in memory by previous stages. |
| 40 | * |
| 41 | * At the moment we implement a heuristic to find the DTB attached to U-Boot: |
| 42 | * U-Boot appends its DTB to the end of the image. Assuming that BL33 is |
| 43 | * U-Boot, try to find the size of the U-Boot image to learn the DTB address. |
| 44 | * The generic ARMv8 U-Boot image contains the load address and its size |
| 45 | * as u64 variables at the beginning of the image. There might be padding |
| 46 | * or other headers before that data, so scan the first 2KB after the BL33 |
| 47 | * entry point to find the load address, which should be followed by the |
| 48 | * size. Adding those together gives us the address of the DTB. |
| 49 | */ |
| 50 | static void *sunxi_find_dtb(void) |
| 51 | { |
| 52 | uint64_t *u_boot_base; |
| 53 | int i; |
| 54 | |
| 55 | u_boot_base = (void *)(SUNXI_DRAM_VIRT_BASE + SUNXI_DRAM_SEC_SIZE); |
| 56 | |
| 57 | for (i = 0; i < 2048 / sizeof(uint64_t); i++) { |
| 58 | uint32_t *dtb_base; |
| 59 | |
| 60 | if (u_boot_base[i] != PLAT_SUNXI_NS_IMAGE_OFFSET) |
| 61 | continue; |
| 62 | |
| 63 | /* Does the suspected U-Boot size look anyhow reasonable? */ |
| 64 | if (u_boot_base[i + 1] >= 256 * 1024 * 1024) |
| 65 | continue; |
| 66 | |
| 67 | /* end of the image: base address + size */ |
| 68 | dtb_base = (void *)((char *)u_boot_base + u_boot_base[i + 1]); |
| 69 | |
| 70 | if (fdt_check_header(dtb_base) != 0) |
| 71 | continue; |
| 72 | |
| 73 | return dtb_base; |
| 74 | } |
| 75 | |
| 76 | return NULL; |
| 77 | } |
| 78 | |
Samuel Holland | b856664 | 2017-08-12 04:07:39 -0500 | [diff] [blame] | 79 | void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, |
| 80 | u_register_t arg2, u_register_t arg3) |
| 81 | { |
| 82 | /* Initialize the debug console as soon as possible */ |
| 83 | console_16550_register(SUNXI_UART0_BASE, SUNXI_UART0_CLK_IN_HZ, |
| 84 | SUNXI_UART0_BAUDRATE, &console); |
| 85 | |
Amit Singh Tomar | 2f37224 | 2018-06-20 00:44:50 +0530 | [diff] [blame] | 86 | #ifdef BL32_BASE |
| 87 | /* Populate entry point information for BL32 */ |
| 88 | SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); |
| 89 | SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); |
| 90 | bl32_image_ep_info.pc = BL32_BASE; |
| 91 | #endif |
| 92 | |
Samuel Holland | b856664 | 2017-08-12 04:07:39 -0500 | [diff] [blame] | 93 | /* Populate entry point information for BL33 */ |
| 94 | SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0); |
| 95 | /* |
| 96 | * Tell BL31 where the non-trusted software image |
| 97 | * is located and the entry state information |
| 98 | */ |
| 99 | bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); |
| 100 | bl33_image_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX, |
| 101 | DISABLE_ALL_EXCEPTIONS); |
| 102 | SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); |
Samuel Holland | 321c0ab | 2017-08-12 04:07:39 -0500 | [diff] [blame] | 103 | |
| 104 | /* Turn off all secondary CPUs */ |
Samuel Holland | c629daf | 2019-02-17 15:33:33 -0600 | [diff] [blame] | 105 | sunxi_disable_secondary_cpus(read_mpidr()); |
Samuel Holland | b856664 | 2017-08-12 04:07:39 -0500 | [diff] [blame] | 106 | } |
| 107 | |
| 108 | void bl31_plat_arch_setup(void) |
| 109 | { |
| 110 | sunxi_configure_mmu_el3(0); |
| 111 | } |
| 112 | |
| 113 | void bl31_platform_setup(void) |
| 114 | { |
Andre Przywara | c2366b9 | 2018-06-22 00:47:08 +0100 | [diff] [blame] | 115 | const char *soc_name; |
| 116 | uint16_t soc_id = sunxi_read_soc_id(); |
Andre Przywara | ea5fa47 | 2018-09-16 02:08:06 +0100 | [diff] [blame] | 117 | void *fdt; |
Andre Przywara | c2366b9 | 2018-06-22 00:47:08 +0100 | [diff] [blame] | 118 | |
| 119 | switch (soc_id) { |
Andre Przywara | 78dca1f | 2018-09-17 00:03:09 +0100 | [diff] [blame] | 120 | case SUNXI_SOC_A64: |
Andre Przywara | c2366b9 | 2018-06-22 00:47:08 +0100 | [diff] [blame] | 121 | soc_name = "A64/H64/R18"; |
| 122 | break; |
Andre Przywara | 78dca1f | 2018-09-17 00:03:09 +0100 | [diff] [blame] | 123 | case SUNXI_SOC_H5: |
Andre Przywara | c2366b9 | 2018-06-22 00:47:08 +0100 | [diff] [blame] | 124 | soc_name = "H5"; |
| 125 | break; |
Andre Przywara | 78dca1f | 2018-09-17 00:03:09 +0100 | [diff] [blame] | 126 | case SUNXI_SOC_H6: |
Andre Przywara | aa26f53 | 2017-12-08 01:27:02 +0000 | [diff] [blame] | 127 | soc_name = "H6"; |
| 128 | break; |
Andre Przywara | c2366b9 | 2018-06-22 00:47:08 +0100 | [diff] [blame] | 129 | default: |
| 130 | soc_name = "unknown"; |
| 131 | break; |
| 132 | } |
| 133 | NOTICE("BL31: Detected Allwinner %s SoC (%04x)\n", soc_name, soc_id); |
| 134 | |
Samuel Holland | b856664 | 2017-08-12 04:07:39 -0500 | [diff] [blame] | 135 | generic_delay_timer_init(); |
| 136 | |
Andre Przywara | ea5fa47 | 2018-09-16 02:08:06 +0100 | [diff] [blame] | 137 | fdt = sunxi_find_dtb(); |
| 138 | if (fdt) { |
| 139 | const char *model; |
| 140 | int length; |
| 141 | |
| 142 | model = fdt_getprop(fdt, 0, "model", &length); |
| 143 | NOTICE("BL31: Found U-Boot DTB at %p, model: %s\n", fdt, |
| 144 | model ?: "unknown"); |
| 145 | } else { |
| 146 | NOTICE("BL31: No DTB found.\n"); |
| 147 | } |
| 148 | |
Samuel Holland | b856664 | 2017-08-12 04:07:39 -0500 | [diff] [blame] | 149 | /* Configure the interrupt controller */ |
| 150 | gicv2_driver_init(&sunxi_gic_data); |
| 151 | gicv2_distif_init(); |
| 152 | gicv2_pcpu_distif_init(); |
| 153 | gicv2_cpuif_enable(); |
| 154 | |
Andre Przywara | 1381547 | 2018-06-01 02:01:39 +0100 | [diff] [blame] | 155 | sunxi_security_setup(); |
| 156 | |
Andre Przywara | e1eb436 | 2018-11-04 23:37:48 +0000 | [diff] [blame] | 157 | /* |
| 158 | * On the A64 U-Boot's SPL sets the bus clocks to some conservative |
| 159 | * values, to work around FEL mode instabilities with SRAM C accesses. |
| 160 | * FEL mode is gone when we reach ATF, so bring the AHB1 bus |
| 161 | * (the "main" bus) clock frequency back to the recommended 200MHz, |
| 162 | * for improved performance. |
| 163 | */ |
| 164 | if (soc_id == SUNXI_SOC_A64) |
| 165 | mmio_write_32(SUNXI_CCU_BASE + 0x54, 0x00003180); |
| 166 | |
| 167 | /* |
| 168 | * U-Boot or the kernel don't setup AHB2, which leaves it at the |
| 169 | * AHB1 frequency (200 MHz, see above). However Allwinner recommends |
| 170 | * 300 MHz, for improved Ethernet and USB performance. Switch the |
| 171 | * clock to use "PLL_PERIPH0 / 2". |
| 172 | */ |
| 173 | if (soc_id == SUNXI_SOC_A64 || soc_id == SUNXI_SOC_H5) |
| 174 | mmio_write_32(SUNXI_CCU_BASE + 0x5c, 0x1); |
| 175 | |
Andre Przywara | 4e4b1e6 | 2018-09-08 19:18:37 +0100 | [diff] [blame] | 176 | sunxi_pmic_setup(soc_id, fdt); |
Icenowy Zheng | 7508bef | 2018-07-21 20:41:12 +0800 | [diff] [blame] | 177 | |
Samuel Holland | b856664 | 2017-08-12 04:07:39 -0500 | [diff] [blame] | 178 | INFO("BL31: Platform setup done\n"); |
| 179 | } |
| 180 | |
| 181 | entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) |
| 182 | { |
| 183 | assert(sec_state_is_valid(type) != 0); |
Amit Singh Tomar | 2f37224 | 2018-06-20 00:44:50 +0530 | [diff] [blame] | 184 | |
| 185 | if (type == NON_SECURE) |
| 186 | return &bl33_image_ep_info; |
| 187 | |
| 188 | if ((type == SECURE) && bl32_image_ep_info.pc) |
| 189 | return &bl32_image_ep_info; |
Samuel Holland | b856664 | 2017-08-12 04:07:39 -0500 | [diff] [blame] | 190 | |
Amit Singh Tomar | 2f37224 | 2018-06-20 00:44:50 +0530 | [diff] [blame] | 191 | return NULL; |
Samuel Holland | b856664 | 2017-08-12 04:07:39 -0500 | [diff] [blame] | 192 | } |