Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 1 | /* |
Daniel Boulby | 60786e7 | 2021-10-22 11:37:34 +0100 | [diff] [blame] | 2 | * Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
Alexei Fedorov | f41355c | 2019-09-13 14:11:59 +0100 | [diff] [blame] | 7 | #include <assert.h> |
Scott Branden | e5dcf98 | 2020-08-25 13:49:32 -0700 | [diff] [blame] | 8 | #include <inttypes.h> |
| 9 | #include <stdint.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 10 | |
Alexei Fedorov | f41355c | 2019-09-13 14:11:59 +0100 | [diff] [blame] | 11 | #include <arch_features.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 12 | #include <arch_helpers.h> |
| 13 | #include <bl32/tsp/tsp.h> |
| 14 | #include <common/bl_common.h> |
| 15 | #include <common/debug.h> |
| 16 | #include <lib/spinlock.h> |
| 17 | #include <plat/common/platform.h> |
Dan Handley | 4fd2f5c | 2014-08-04 11:41:20 +0100 | [diff] [blame] | 18 | #include <platform_tsp.h> |
Dan Handley | e2c27f5 | 2014-08-01 17:58:27 +0100 | [diff] [blame] | 19 | #include "tsp_private.h" |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 20 | |
Achin Gupta | 6b4ec24 | 2021-10-04 20:13:36 +0100 | [diff] [blame] | 21 | #include <platform_def.h> |
Antonio Nino Diaz | e61ece0 | 2019-02-26 11:41:03 +0000 | [diff] [blame] | 22 | |
| 23 | /******************************************************************************* |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 24 | * TSP main entry point where it gets the opportunity to initialize its secure |
| 25 | * state/applications. Once the state is initialized, it must return to the |
Andrew Thoelke | 891c4ca | 2014-05-20 21:43:27 +0100 | [diff] [blame] | 26 | * SPD with a pointer to the 'tsp_vector_table' jump table. |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 27 | ******************************************************************************/ |
| 28 | uint64_t tsp_main(void) |
| 29 | { |
Dan Handley | 91b624e | 2014-07-29 17:14:00 +0100 | [diff] [blame] | 30 | NOTICE("TSP: %s\n", version_string); |
| 31 | NOTICE("TSP: %s\n", build_message); |
Sandrine Bailleux | bdba5e5 | 2016-06-16 14:24:26 +0100 | [diff] [blame] | 32 | INFO("TSP: Total memory base : 0x%lx\n", (unsigned long) BL32_BASE); |
| 33 | INFO("TSP: Total memory size : 0x%lx bytes\n", BL32_TOTAL_SIZE); |
Dan Handley | 91b624e | 2014-07-29 17:14:00 +0100 | [diff] [blame] | 34 | |
Soby Mathew | da43b66 | 2015-07-08 21:45:46 +0100 | [diff] [blame] | 35 | uint32_t linear_id = plat_my_core_pos(); |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 36 | |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 37 | /* Initialize the platform */ |
Dan Handley | 4fd2f5c | 2014-08-04 11:41:20 +0100 | [diff] [blame] | 38 | tsp_platform_setup(); |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 39 | |
| 40 | /* Initialize secure/applications state here */ |
Achin Gupta | bbc33f2 | 2014-05-09 13:33:42 +0100 | [diff] [blame] | 41 | tsp_generic_timer_start(); |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 42 | |
| 43 | /* Update this cpu's statistics */ |
| 44 | tsp_stats[linear_id].smc_count++; |
| 45 | tsp_stats[linear_id].eret_count++; |
| 46 | tsp_stats[linear_id].cpu_on_count++; |
| 47 | |
Soby Mathew | da43b66 | 2015-07-08 21:45:46 +0100 | [diff] [blame] | 48 | INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu on requests\n", |
| 49 | read_mpidr(), |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 50 | tsp_stats[linear_id].smc_count, |
| 51 | tsp_stats[linear_id].eret_count, |
| 52 | tsp_stats[linear_id].cpu_on_count); |
Govindraj Raja | 55ca30d | 2023-05-22 13:22:42 -0500 | [diff] [blame] | 53 | |
| 54 | console_flush(); |
Andrew Thoelke | 891c4ca | 2014-05-20 21:43:27 +0100 | [diff] [blame] | 55 | return (uint64_t) &tsp_vector_table; |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 56 | } |
| 57 | |
| 58 | /******************************************************************************* |
| 59 | * This function performs any remaining book keeping in the test secure payload |
| 60 | * after this cpu's architectural state has been setup in response to an earlier |
| 61 | * psci cpu_on request. |
| 62 | ******************************************************************************/ |
Achin Gupta | 6b4ec24 | 2021-10-04 20:13:36 +0100 | [diff] [blame] | 63 | smc_args_t *tsp_cpu_on_main(void) |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 64 | { |
Soby Mathew | da43b66 | 2015-07-08 21:45:46 +0100 | [diff] [blame] | 65 | uint32_t linear_id = plat_my_core_pos(); |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 66 | |
Achin Gupta | bbc33f2 | 2014-05-09 13:33:42 +0100 | [diff] [blame] | 67 | /* Initialize secure/applications state here */ |
| 68 | tsp_generic_timer_start(); |
| 69 | |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 70 | /* Update this cpu's statistics */ |
| 71 | tsp_stats[linear_id].smc_count++; |
| 72 | tsp_stats[linear_id].eret_count++; |
| 73 | tsp_stats[linear_id].cpu_on_count++; |
| 74 | |
Soby Mathew | da43b66 | 2015-07-08 21:45:46 +0100 | [diff] [blame] | 75 | INFO("TSP: cpu 0x%lx turned on\n", read_mpidr()); |
| 76 | INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu on requests\n", |
| 77 | read_mpidr(), |
Dan Handley | 91b624e | 2014-07-29 17:14:00 +0100 | [diff] [blame] | 78 | tsp_stats[linear_id].smc_count, |
| 79 | tsp_stats[linear_id].eret_count, |
| 80 | tsp_stats[linear_id].cpu_on_count); |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 81 | /* Indicate to the SPD that we have completed turned ourselves on */ |
| 82 | return set_smc_args(TSP_ON_DONE, 0, 0, 0, 0, 0, 0, 0); |
| 83 | } |
| 84 | |
| 85 | /******************************************************************************* |
| 86 | * This function performs any remaining book keeping in the test secure payload |
| 87 | * before this cpu is turned off in response to a psci cpu_off request. |
| 88 | ******************************************************************************/ |
Achin Gupta | 6b4ec24 | 2021-10-04 20:13:36 +0100 | [diff] [blame] | 89 | smc_args_t *tsp_cpu_off_main(uint64_t arg0, |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 90 | uint64_t arg1, |
| 91 | uint64_t arg2, |
| 92 | uint64_t arg3, |
| 93 | uint64_t arg4, |
| 94 | uint64_t arg5, |
| 95 | uint64_t arg6, |
| 96 | uint64_t arg7) |
| 97 | { |
Soby Mathew | da43b66 | 2015-07-08 21:45:46 +0100 | [diff] [blame] | 98 | uint32_t linear_id = plat_my_core_pos(); |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 99 | |
Achin Gupta | bbc33f2 | 2014-05-09 13:33:42 +0100 | [diff] [blame] | 100 | /* |
| 101 | * This cpu is being turned off, so disable the timer to prevent the |
| 102 | * secure timer interrupt from interfering with power down. A pending |
| 103 | * interrupt will be lost but we do not care as we are turning off. |
| 104 | */ |
| 105 | tsp_generic_timer_stop(); |
| 106 | |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 107 | /* Update this cpu's statistics */ |
| 108 | tsp_stats[linear_id].smc_count++; |
| 109 | tsp_stats[linear_id].eret_count++; |
| 110 | tsp_stats[linear_id].cpu_off_count++; |
| 111 | |
Soby Mathew | da43b66 | 2015-07-08 21:45:46 +0100 | [diff] [blame] | 112 | INFO("TSP: cpu 0x%lx off request\n", read_mpidr()); |
| 113 | INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu off requests\n", |
| 114 | read_mpidr(), |
Dan Handley | 91b624e | 2014-07-29 17:14:00 +0100 | [diff] [blame] | 115 | tsp_stats[linear_id].smc_count, |
| 116 | tsp_stats[linear_id].eret_count, |
| 117 | tsp_stats[linear_id].cpu_off_count); |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 118 | |
Achin Gupta | 607084e | 2014-02-09 18:24:19 +0000 | [diff] [blame] | 119 | /* Indicate to the SPD that we have completed this request */ |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 120 | return set_smc_args(TSP_OFF_DONE, 0, 0, 0, 0, 0, 0, 0); |
| 121 | } |
| 122 | |
| 123 | /******************************************************************************* |
| 124 | * This function performs any book keeping in the test secure payload before |
| 125 | * this cpu's architectural state is saved in response to an earlier psci |
| 126 | * cpu_suspend request. |
| 127 | ******************************************************************************/ |
Achin Gupta | 6b4ec24 | 2021-10-04 20:13:36 +0100 | [diff] [blame] | 128 | smc_args_t *tsp_cpu_suspend_main(uint64_t arg0, |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 129 | uint64_t arg1, |
| 130 | uint64_t arg2, |
| 131 | uint64_t arg3, |
| 132 | uint64_t arg4, |
| 133 | uint64_t arg5, |
| 134 | uint64_t arg6, |
| 135 | uint64_t arg7) |
| 136 | { |
Soby Mathew | da43b66 | 2015-07-08 21:45:46 +0100 | [diff] [blame] | 137 | uint32_t linear_id = plat_my_core_pos(); |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 138 | |
Achin Gupta | bbc33f2 | 2014-05-09 13:33:42 +0100 | [diff] [blame] | 139 | /* |
| 140 | * Save the time context and disable it to prevent the secure timer |
| 141 | * interrupt from interfering with wakeup from the suspend state. |
| 142 | */ |
| 143 | tsp_generic_timer_save(); |
| 144 | tsp_generic_timer_stop(); |
| 145 | |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 146 | /* Update this cpu's statistics */ |
| 147 | tsp_stats[linear_id].smc_count++; |
| 148 | tsp_stats[linear_id].eret_count++; |
| 149 | tsp_stats[linear_id].cpu_suspend_count++; |
| 150 | |
Sandrine Bailleux | 8723adf | 2015-02-05 15:42:31 +0000 | [diff] [blame] | 151 | INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu suspend requests\n", |
Soby Mathew | da43b66 | 2015-07-08 21:45:46 +0100 | [diff] [blame] | 152 | read_mpidr(), |
Dan Handley | 91b624e | 2014-07-29 17:14:00 +0100 | [diff] [blame] | 153 | tsp_stats[linear_id].smc_count, |
| 154 | tsp_stats[linear_id].eret_count, |
| 155 | tsp_stats[linear_id].cpu_suspend_count); |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 156 | |
Achin Gupta | 607084e | 2014-02-09 18:24:19 +0000 | [diff] [blame] | 157 | /* Indicate to the SPD that we have completed this request */ |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 158 | return set_smc_args(TSP_SUSPEND_DONE, 0, 0, 0, 0, 0, 0, 0); |
| 159 | } |
| 160 | |
| 161 | /******************************************************************************* |
| 162 | * This function performs any book keeping in the test secure payload after this |
| 163 | * cpu's architectural state has been restored after wakeup from an earlier psci |
| 164 | * cpu_suspend request. |
| 165 | ******************************************************************************/ |
Achin Gupta | 6b4ec24 | 2021-10-04 20:13:36 +0100 | [diff] [blame] | 166 | smc_args_t *tsp_cpu_resume_main(uint64_t max_off_pwrlvl, |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 167 | uint64_t arg1, |
| 168 | uint64_t arg2, |
| 169 | uint64_t arg3, |
| 170 | uint64_t arg4, |
| 171 | uint64_t arg5, |
| 172 | uint64_t arg6, |
| 173 | uint64_t arg7) |
| 174 | { |
Soby Mathew | da43b66 | 2015-07-08 21:45:46 +0100 | [diff] [blame] | 175 | uint32_t linear_id = plat_my_core_pos(); |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 176 | |
Achin Gupta | bbc33f2 | 2014-05-09 13:33:42 +0100 | [diff] [blame] | 177 | /* Restore the generic timer context */ |
| 178 | tsp_generic_timer_restore(); |
| 179 | |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 180 | /* Update this cpu's statistics */ |
| 181 | tsp_stats[linear_id].smc_count++; |
| 182 | tsp_stats[linear_id].eret_count++; |
| 183 | tsp_stats[linear_id].cpu_resume_count++; |
| 184 | |
Scott Branden | e5dcf98 | 2020-08-25 13:49:32 -0700 | [diff] [blame] | 185 | INFO("TSP: cpu 0x%lx resumed. maximum off power level %" PRId64 "\n", |
Achin Gupta | 9a0ff9b | 2015-09-07 20:43:27 +0100 | [diff] [blame] | 186 | read_mpidr(), max_off_pwrlvl); |
Manish Pandey | c4b47a2 | 2020-03-06 14:36:25 +0000 | [diff] [blame] | 187 | INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu resume requests\n", |
Soby Mathew | da43b66 | 2015-07-08 21:45:46 +0100 | [diff] [blame] | 188 | read_mpidr(), |
Dan Handley | 91b624e | 2014-07-29 17:14:00 +0100 | [diff] [blame] | 189 | tsp_stats[linear_id].smc_count, |
| 190 | tsp_stats[linear_id].eret_count, |
Manish Pandey | c4b47a2 | 2020-03-06 14:36:25 +0000 | [diff] [blame] | 191 | tsp_stats[linear_id].cpu_resume_count); |
Achin Gupta | 607084e | 2014-02-09 18:24:19 +0000 | [diff] [blame] | 192 | /* Indicate to the SPD that we have completed this request */ |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 193 | return set_smc_args(TSP_RESUME_DONE, 0, 0, 0, 0, 0, 0, 0); |
| 194 | } |
| 195 | |
| 196 | /******************************************************************************* |
| 197 | * TSP fast smc handler. The secure monitor jumps to this function by |
| 198 | * doing the ERET after populating X0-X7 registers. The arguments are received |
| 199 | * in the function arguments in order. Once the service is rendered, this |
Soby Mathew | 9f71f70 | 2014-05-09 20:49:17 +0100 | [diff] [blame] | 200 | * function returns to Secure Monitor by raising SMC. |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 201 | ******************************************************************************/ |
Achin Gupta | 6b4ec24 | 2021-10-04 20:13:36 +0100 | [diff] [blame] | 202 | smc_args_t *tsp_smc_handler(uint64_t func, |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 203 | uint64_t arg1, |
| 204 | uint64_t arg2, |
| 205 | uint64_t arg3, |
| 206 | uint64_t arg4, |
| 207 | uint64_t arg5, |
| 208 | uint64_t arg6, |
| 209 | uint64_t arg7) |
| 210 | { |
Alexei Fedorov | 7d616ee | 2020-11-13 12:36:49 +0000 | [diff] [blame] | 211 | uint128_t service_args; |
| 212 | uint64_t service_arg0; |
| 213 | uint64_t service_arg1; |
Achin Gupta | 916a2c1 | 2014-02-09 23:11:46 +0000 | [diff] [blame] | 214 | uint64_t results[2]; |
Soby Mathew | da43b66 | 2015-07-08 21:45:46 +0100 | [diff] [blame] | 215 | uint32_t linear_id = plat_my_core_pos(); |
Daniel Boulby | 60786e7 | 2021-10-22 11:37:34 +0100 | [diff] [blame] | 216 | u_register_t dit; |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 217 | |
Achin Gupta | 916a2c1 | 2014-02-09 23:11:46 +0000 | [diff] [blame] | 218 | /* Update this cpu's statistics */ |
| 219 | tsp_stats[linear_id].smc_count++; |
| 220 | tsp_stats[linear_id].eret_count++; |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 221 | |
Scott Branden | e5dcf98 | 2020-08-25 13:49:32 -0700 | [diff] [blame] | 222 | INFO("TSP: cpu 0x%lx received %s smc 0x%" PRIx64 "\n", read_mpidr(), |
David Cunado | 28f69ab | 2017-04-05 11:34:03 +0100 | [diff] [blame] | 223 | ((func >> 31) & 1) == 1 ? "fast" : "yielding", |
Dan Handley | 91b624e | 2014-07-29 17:14:00 +0100 | [diff] [blame] | 224 | func); |
Soby Mathew | da43b66 | 2015-07-08 21:45:46 +0100 | [diff] [blame] | 225 | INFO("TSP: cpu 0x%lx: %d smcs, %d erets\n", read_mpidr(), |
Dan Handley | 91b624e | 2014-07-29 17:14:00 +0100 | [diff] [blame] | 226 | tsp_stats[linear_id].smc_count, |
| 227 | tsp_stats[linear_id].eret_count); |
Achin Gupta | 916a2c1 | 2014-02-09 23:11:46 +0000 | [diff] [blame] | 228 | |
| 229 | /* Render secure services and obtain results here */ |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 230 | results[0] = arg1; |
| 231 | results[1] = arg2; |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 232 | |
| 233 | /* |
Alexei Fedorov | 7d616ee | 2020-11-13 12:36:49 +0000 | [diff] [blame] | 234 | * Request a service back from dispatcher/secure monitor. |
| 235 | * This call returns and thereafter resumes execution. |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 236 | */ |
Alexei Fedorov | 7d616ee | 2020-11-13 12:36:49 +0000 | [diff] [blame] | 237 | service_args = tsp_get_magic(); |
| 238 | service_arg0 = (uint64_t)service_args; |
| 239 | service_arg1 = (uint64_t)(service_args >> 64U); |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 240 | |
Justin Chadwell | 1c7c13a | 2019-07-18 14:25:33 +0100 | [diff] [blame] | 241 | #if CTX_INCLUDE_MTE_REGS |
| 242 | /* |
| 243 | * Write a dummy value to an MTE register, to simulate usage in the |
| 244 | * secure world |
| 245 | */ |
| 246 | write_gcr_el1(0x99); |
| 247 | #endif |
| 248 | |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 249 | /* Determine the function to perform based on the function ID */ |
Soby Mathew | 9f71f70 | 2014-05-09 20:49:17 +0100 | [diff] [blame] | 250 | switch (TSP_BARE_FID(func)) { |
| 251 | case TSP_ADD: |
Alexei Fedorov | 7d616ee | 2020-11-13 12:36:49 +0000 | [diff] [blame] | 252 | results[0] += service_arg0; |
| 253 | results[1] += service_arg1; |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 254 | break; |
Soby Mathew | 9f71f70 | 2014-05-09 20:49:17 +0100 | [diff] [blame] | 255 | case TSP_SUB: |
Alexei Fedorov | 7d616ee | 2020-11-13 12:36:49 +0000 | [diff] [blame] | 256 | results[0] -= service_arg0; |
| 257 | results[1] -= service_arg1; |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 258 | break; |
Soby Mathew | 9f71f70 | 2014-05-09 20:49:17 +0100 | [diff] [blame] | 259 | case TSP_MUL: |
Alexei Fedorov | 7d616ee | 2020-11-13 12:36:49 +0000 | [diff] [blame] | 260 | results[0] *= service_arg0; |
| 261 | results[1] *= service_arg1; |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 262 | break; |
Soby Mathew | 9f71f70 | 2014-05-09 20:49:17 +0100 | [diff] [blame] | 263 | case TSP_DIV: |
Alexei Fedorov | 7d616ee | 2020-11-13 12:36:49 +0000 | [diff] [blame] | 264 | results[0] /= service_arg0 ? service_arg0 : 1; |
| 265 | results[1] /= service_arg1 ? service_arg1 : 1; |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 266 | break; |
Daniel Boulby | 60786e7 | 2021-10-22 11:37:34 +0100 | [diff] [blame] | 267 | case TSP_CHECK_DIT: |
Andre Przywara | 1f55c41 | 2023-01-26 16:47:52 +0000 | [diff] [blame] | 268 | if (!is_feat_dit_supported()) { |
Daniel Boulby | 60786e7 | 2021-10-22 11:37:34 +0100 | [diff] [blame] | 269 | ERROR("DIT not supported\n"); |
Daniel Boulby | 60786e7 | 2021-10-22 11:37:34 +0100 | [diff] [blame] | 270 | results[0] = 0; |
| 271 | results[1] = 0xffff; |
| 272 | break; |
| 273 | } |
| 274 | dit = read_dit(); |
| 275 | results[0] = dit == service_arg0; |
| 276 | results[1] = dit; |
| 277 | /* Toggle the dit bit */ |
| 278 | write_dit(service_arg0 != 0U ? 0 : DIT_BIT); |
| 279 | break; |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 280 | default: |
| 281 | break; |
| 282 | } |
| 283 | |
Soby Mathew | 9f71f70 | 2014-05-09 20:49:17 +0100 | [diff] [blame] | 284 | return set_smc_args(func, 0, |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 285 | results[0], |
| 286 | results[1], |
Soby Mathew | 9f71f70 | 2014-05-09 20:49:17 +0100 | [diff] [blame] | 287 | 0, 0, 0, 0); |
Achin Gupta | 7c88f3f | 2014-02-18 18:09:12 +0000 | [diff] [blame] | 288 | } |