blob: 3613614255ac3879d860f381c633bcd6fd549d07 [file] [log] [blame]
Soby Mathewb911cc72017-02-13 12:46:28 +00001/*
2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#ifndef __EP_INFO_H__
32#define __EP_INFO_H__
33
34#include <param_header.h>
35
36#define SECURE 0x0
37#define NON_SECURE 0x1
38#define sec_state_is_valid(s) (((s) == SECURE) || ((s) == NON_SECURE))
39
40/*******************************************************************************
41 * Constants that allow assembler code to access members of and the
42 * 'entry_point_info' structure at their correct offsets.
43 ******************************************************************************/
44#define ENTRY_POINT_INFO_PC_OFFSET 0x08
45#ifdef AARCH32
46#define ENTRY_POINT_INFO_ARGS_OFFSET 0x10
47#else
48#define ENTRY_POINT_INFO_ARGS_OFFSET 0x18
49#endif
50
51/* The following are used to set/get image attributes. */
52#define PARAM_EP_SECURITY_MASK (0x1)
53
54#define GET_SECURITY_STATE(x) (x & PARAM_EP_SECURITY_MASK)
55#define SET_SECURITY_STATE(x, security) \
56 ((x) = ((x) & ~PARAM_EP_SECURITY_MASK) | (security))
57
58#define EP_EE_MASK 0x2
59#define EP_EE_LITTLE 0x0
60#define EP_EE_BIG 0x2
61#define EP_GET_EE(x) (x & EP_EE_MASK)
62#define EP_SET_EE(x, ee) ((x) = ((x) & ~EP_EE_MASK) | (ee))
63
64#define EP_ST_MASK 0x4
65#define EP_ST_DISABLE 0x0
66#define EP_ST_ENABLE 0x4
67#define EP_GET_ST(x) (x & EP_ST_MASK)
68#define EP_SET_ST(x, ee) ((x) = ((x) & ~EP_ST_MASK) | (ee))
69
70#define EP_EXE_MASK 0x8
71#define NON_EXECUTABLE 0x0
72#define EXECUTABLE 0x8
73#define EP_GET_EXE(x) (x & EP_EXE_MASK)
74#define EP_SET_EXE(x, ee) ((x) = ((x) & ~EP_EXE_MASK) | (ee))
75
76#define EP_FIRST_EXE_MASK 0x10
77#define EP_FIRST_EXE 0x10
78#define EP_GET_FIRST_EXE(x) ((x) & EP_FIRST_EXE_MASK)
79#define EP_SET_FIRST_EXE(x, ee) ((x) = ((x) & ~EP_FIRST_EXE_MASK) | (ee))
80
81#ifndef __ASSEMBLY__
82
83#include <cassert.h>
84#include <types.h>
85
86typedef struct aapcs64_params {
87 u_register_t arg0;
88 u_register_t arg1;
89 u_register_t arg2;
90 u_register_t arg3;
91 u_register_t arg4;
92 u_register_t arg5;
93 u_register_t arg6;
94 u_register_t arg7;
95} aapcs64_params_t;
96
97typedef struct aapcs32_params {
98 u_register_t arg0;
99 u_register_t arg1;
100 u_register_t arg2;
101 u_register_t arg3;
102} aapcs32_params_t;
103
104/*****************************************************************************
105 * This structure represents the superset of information needed while
106 * switching exception levels. The only two mechanisms to do so are
107 * ERET & SMC. Security state is indicated using bit zero of header
108 * attribute
109 * NOTE: BL1 expects entrypoint followed by spsr at an offset from the start
110 * of this structure defined by the macro `ENTRY_POINT_INFO_PC_OFFSET` while
111 * processing SMC to jump to BL31.
112 *****************************************************************************/
113typedef struct entry_point_info {
114 param_header_t h;
115 uintptr_t pc;
116 uint32_t spsr;
117#ifdef AARCH32
118 aapcs32_params_t args;
119#else
120 aapcs64_params_t args;
121#endif
122} entry_point_info_t;
123
124/*
125 * Compile time assertions related to the 'entry_point_info' structure to
126 * ensure that the assembler and the compiler view of the offsets of
127 * the structure members is the same.
128 */
129CASSERT(ENTRY_POINT_INFO_PC_OFFSET ==
130 __builtin_offsetof(entry_point_info_t, pc), \
131 assert_BL31_pc_offset_mismatch);
132
133CASSERT(ENTRY_POINT_INFO_ARGS_OFFSET == \
134 __builtin_offsetof(entry_point_info_t, args), \
135 assert_BL31_args_offset_mismatch);
136
137CASSERT(sizeof(uintptr_t) ==
138 __builtin_offsetof(entry_point_info_t, spsr) - \
139 __builtin_offsetof(entry_point_info_t, pc), \
140 assert_entrypoint_and_spsr_should_be_adjacent);
141
142#endif /*__ASSEMBLY__*/
143
144#endif /* __EP_INFO_H__ */
145