blob: e341cfd7da58c09002f25f55829ce21fe569bf0d [file] [log] [blame]
Dan Handleye2c27f52014-08-01 17:58:27 +01001/*
2 * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#ifndef __TSP_PRIVATE_H__
32#define __TSP_PRIVATE_H__
33
34/* Definitions to help the assembler access the SMC/ERET args structure */
35#define TSP_ARGS_SIZE 0x40
36#define TSP_ARG0 0x0
37#define TSP_ARG1 0x8
38#define TSP_ARG2 0x10
39#define TSP_ARG3 0x18
40#define TSP_ARG4 0x20
41#define TSP_ARG5 0x28
42#define TSP_ARG6 0x30
43#define TSP_ARG7 0x38
44#define TSP_ARGS_END 0x40
45
46
47#ifndef __ASSEMBLY__
48
49#include <cassert.h>
50#include <platform_def.h> /* For CACHE_WRITEBACK_GRANULE */
51#include <spinlock.h>
52#include <stdint.h>
53#include <tsp.h>
54
55
56typedef struct work_statistics {
Soby Mathewbec98512015-09-03 18:29:38 +010057 /* Number of s-el1 interrupts on this cpu */
58 uint32_t sel1_intr_count;
Soby Mathewbc912822015-09-22 12:01:18 +010059 /* Number of non s-el1 interrupts on this cpu which preempted TSP */
60 uint32_t preempt_intr_count;
Soby Mathewbec98512015-09-03 18:29:38 +010061 /* Number of sync s-el1 interrupts on this cpu */
62 uint32_t sync_sel1_intr_count;
63 /* Number of s-el1 interrupts returns on this cpu */
64 uint32_t sync_sel1_intr_ret_count;
Dan Handleye2c27f52014-08-01 17:58:27 +010065 uint32_t smc_count; /* Number of returns on this cpu */
66 uint32_t eret_count; /* Number of entries on this cpu */
67 uint32_t cpu_on_count; /* Number of cpu on requests */
68 uint32_t cpu_off_count; /* Number of cpu off requests */
69 uint32_t cpu_suspend_count; /* Number of cpu suspend requests */
70 uint32_t cpu_resume_count; /* Number of cpu resume requests */
71} __aligned(CACHE_WRITEBACK_GRANULE) work_statistics_t;
72
73typedef struct tsp_args {
74 uint64_t _regs[TSP_ARGS_END >> 3];
75} __aligned(CACHE_WRITEBACK_GRANULE) tsp_args_t;
76
77/* Macros to access members of the above structure using their offsets */
78#define read_sp_arg(args, offset) ((args)->_regs[offset >> 3])
79#define write_sp_arg(args, offset, val) (((args)->_regs[offset >> 3]) \
80 = val)
81/*
82 * Ensure that the assembler's view of the size of the tsp_args is the
83 * same as the compilers
84 */
85CASSERT(TSP_ARGS_SIZE == sizeof(tsp_args_t), assert_sp_args_size_mismatch);
86
87void tsp_get_magic(uint64_t args[4]);
88
89tsp_args_t *tsp_cpu_resume_main(uint64_t arg0,
90 uint64_t arg1,
91 uint64_t arg2,
92 uint64_t arg3,
93 uint64_t arg4,
94 uint64_t arg5,
95 uint64_t arg6,
96 uint64_t arg7);
97tsp_args_t *tsp_cpu_suspend_main(uint64_t arg0,
98 uint64_t arg1,
99 uint64_t arg2,
100 uint64_t arg3,
101 uint64_t arg4,
102 uint64_t arg5,
103 uint64_t arg6,
104 uint64_t arg7);
105tsp_args_t *tsp_cpu_on_main(void);
106tsp_args_t *tsp_cpu_off_main(uint64_t arg0,
107 uint64_t arg1,
108 uint64_t arg2,
109 uint64_t arg3,
110 uint64_t arg4,
111 uint64_t arg5,
112 uint64_t arg6,
113 uint64_t arg7);
114
115/* Generic Timer functions */
116void tsp_generic_timer_start(void);
117void tsp_generic_timer_handler(void);
118void tsp_generic_timer_stop(void);
119void tsp_generic_timer_save(void);
120void tsp_generic_timer_restore(void);
121
Soby Mathewbec98512015-09-03 18:29:38 +0100122/* S-EL1 interrupt management functions */
123void tsp_update_sync_sel1_intr_stats(uint32_t type, uint64_t elr_el3);
Dan Handleye2c27f52014-08-01 17:58:27 +0100124
125
126/* Data structure to keep track of TSP statistics */
127extern spinlock_t console_lock;
128extern work_statistics_t tsp_stats[PLATFORM_CORE_COUNT];
129
130/* Vector table of jumps */
131extern tsp_vectors_t tsp_vector_table;
132
133
134#endif /* __ASSEMBLY__ */
135
136#endif /* __TSP_PRIVATE_H__ */
137