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Dan Handley9df48042015-03-19 18:58:55 +00001/*
Antonio Nino Diaz719bf852017-02-23 17:22:58 +00002 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +00003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <arch.h>
32#include <arm_def.h>
Antonio Nino Diazf09d0032017-04-11 14:04:56 +010033#include <arm_xlat_tables.h>
Dan Handley9df48042015-03-19 18:58:55 +000034#include <bl_common.h>
Dan Handley9df48042015-03-19 18:58:55 +000035#include <console.h>
36#include <platform_def.h>
37#include <plat_arm.h>
Juan Castillob6132f12015-10-06 14:01:35 +010038#include <sp805.h>
Sandrine Bailleux28ee10f2016-06-15 15:44:27 +010039#include <utils.h>
Sandrine Bailleuxd7c47502015-10-02 09:32:35 +010040#include "../../../bl1/bl1_private.h"
Dan Handley9df48042015-03-19 18:58:55 +000041
Dan Handley9df48042015-03-19 18:58:55 +000042/* Weak definitions may be overridden in specific ARM standard platform */
43#pragma weak bl1_early_platform_setup
44#pragma weak bl1_plat_arch_setup
45#pragma weak bl1_platform_setup
46#pragma weak bl1_plat_sec_mem_layout
Yatharth Kocharede39cb2016-11-14 12:01:04 +000047#pragma weak bl1_plat_prepare_exit
Dan Handley9df48042015-03-19 18:58:55 +000048
49
50/* Data structure which holds the extents of the trusted SRAM for BL1*/
51static meminfo_t bl1_tzram_layout;
52
53meminfo_t *bl1_plat_sec_mem_layout(void)
54{
55 return &bl1_tzram_layout;
56}
57
58/*******************************************************************************
59 * BL1 specific platform actions shared between ARM standard platforms.
60 ******************************************************************************/
61void arm_bl1_early_platform_setup(void)
62{
Dan Handley9df48042015-03-19 18:58:55 +000063
Juan Castillob6132f12015-10-06 14:01:35 +010064#if !ARM_DISABLE_TRUSTED_WDOG
65 /* Enable watchdog */
66 sp805_start(ARM_SP805_TWDG_BASE, ARM_TWDG_LOAD_VAL);
67#endif
68
Dan Handley9df48042015-03-19 18:58:55 +000069 /* Initialize the console to provide early debug support */
70 console_init(PLAT_ARM_BOOT_UART_BASE, PLAT_ARM_BOOT_UART_CLK_IN_HZ,
71 ARM_CONSOLE_BAUDRATE);
72
73 /* Allow BL1 to see the whole Trusted RAM */
74 bl1_tzram_layout.total_base = ARM_BL_RAM_BASE;
75 bl1_tzram_layout.total_size = ARM_BL_RAM_SIZE;
76
Yatharth Kocharf9a0f162016-09-13 17:07:57 +010077#if !LOAD_IMAGE_V2
Dan Handley9df48042015-03-19 18:58:55 +000078 /* Calculate how much RAM BL1 is using and how much remains free */
79 bl1_tzram_layout.free_base = ARM_BL_RAM_BASE;
80 bl1_tzram_layout.free_size = ARM_BL_RAM_SIZE;
81 reserve_mem(&bl1_tzram_layout.free_base,
82 &bl1_tzram_layout.free_size,
83 BL1_RAM_BASE,
Yatharth Kocharf9a0f162016-09-13 17:07:57 +010084 BL1_RAM_LIMIT - BL1_RAM_BASE);
85#endif /* LOAD_IMAGE_V2 */
Dan Handley9df48042015-03-19 18:58:55 +000086}
87
88void bl1_early_platform_setup(void)
89{
90 arm_bl1_early_platform_setup();
91
92 /*
Vikram Kanigirifbb13012016-02-15 11:54:14 +000093 * Initialize Interconnect for this cluster during cold boot.
Dan Handley9df48042015-03-19 18:58:55 +000094 * No need for locks as no other CPU is active.
95 */
Vikram Kanigirifbb13012016-02-15 11:54:14 +000096 plat_arm_interconnect_init();
Dan Handley9df48042015-03-19 18:58:55 +000097 /*
Vikram Kanigirifbb13012016-02-15 11:54:14 +000098 * Enable Interconnect coherency for the primary CPU's cluster.
Dan Handley9df48042015-03-19 18:58:55 +000099 */
Vikram Kanigirifbb13012016-02-15 11:54:14 +0000100 plat_arm_interconnect_enter_coherency();
Dan Handley9df48042015-03-19 18:58:55 +0000101}
102
103/******************************************************************************
104 * Perform the very early platform specific architecture setup shared between
105 * ARM standard platforms. This only does basic initialization. Later
106 * architectural setup (bl1_arch_setup()) does not do anything platform
107 * specific.
108 *****************************************************************************/
109void arm_bl1_plat_arch_setup(void)
110{
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +0100111 arm_setup_page_tables(bl1_tzram_layout.total_base,
Dan Handley9df48042015-03-19 18:58:55 +0000112 bl1_tzram_layout.total_size,
Sandrine Bailleuxecdc4d32016-07-08 14:38:16 +0100113 BL_CODE_BASE,
Masahiro Yamada51bef612017-01-18 02:10:08 +0900114 BL1_CODE_END,
Sandrine Bailleuxecdc4d32016-07-08 14:38:16 +0100115 BL1_RO_DATA_BASE,
Masahiro Yamada51bef612017-01-18 02:10:08 +0900116 BL1_RO_DATA_END
Dan Handley9df48042015-03-19 18:58:55 +0000117#if USE_COHERENT_MEM
Masahiro Yamada0fac5af2016-12-28 16:11:41 +0900118 , BL_COHERENT_RAM_BASE,
119 BL_COHERENT_RAM_END
Dan Handley9df48042015-03-19 18:58:55 +0000120#endif
121 );
Yatharth Kochar88ac53b2016-07-04 11:03:49 +0100122#ifdef AARCH32
123 enable_mmu_secure(0);
124#else
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +0100125 enable_mmu_el3(0);
Yatharth Kochar88ac53b2016-07-04 11:03:49 +0100126#endif /* AARCH32 */
Dan Handley9df48042015-03-19 18:58:55 +0000127}
128
129void bl1_plat_arch_setup(void)
130{
131 arm_bl1_plat_arch_setup();
132}
133
134/*
135 * Perform the platform specific architecture setup shared between
136 * ARM standard platforms.
137 */
138void arm_bl1_platform_setup(void)
139{
140 /* Initialise the IO layer and register platform IO devices */
141 plat_arm_io_setup();
142}
143
144void bl1_platform_setup(void)
145{
146 arm_bl1_platform_setup();
147}
148
Sandrine Bailleux03897bb2015-11-26 16:31:34 +0000149void bl1_plat_prepare_exit(entry_point_info_t *ep_info)
150{
Juan Castillob6132f12015-10-06 14:01:35 +0100151#if !ARM_DISABLE_TRUSTED_WDOG
152 /* Disable watchdog before leaving BL1 */
153 sp805_stop(ARM_SP805_TWDG_BASE);
154#endif
155
Sandrine Bailleux03897bb2015-11-26 16:31:34 +0000156#ifdef EL3_PAYLOAD_BASE
157 /*
158 * Program the EL3 payload's entry point address into the CPUs mailbox
159 * in order to release secondary CPUs from their holding pen and make
160 * them jump there.
161 */
162 arm_program_trusted_mailbox(ep_info->pc);
163 dsbsy();
164 sev();
165#endif
166}