Yatharth Kochar | 2694cba | 2016-11-14 12:00:41 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #include <arch.h> |
| 32 | #include <asm_macros.S> |
| 33 | #include <bl_common.h> |
| 34 | #include <cortex_a53.h> |
| 35 | #include <cortex_a57.h> |
| 36 | #include <cortex_a72.h> |
| 37 | #include <v2m_def.h> |
| 38 | #include "../juno_def.h" |
| 39 | |
| 40 | |
| 41 | .globl plat_reset_handler |
| 42 | .globl plat_arm_calc_core_pos |
| 43 | |
| 44 | #define JUNO_REVISION(rev) REV_JUNO_R##rev |
| 45 | #define JUNO_HANDLER(rev) plat_reset_handler_juno_r##rev |
| 46 | #define JUMP_TO_HANDLER_IF_JUNO_R(revision) \ |
| 47 | jump_to_handler JUNO_REVISION(revision), JUNO_HANDLER(revision) |
| 48 | |
| 49 | /* -------------------------------------------------------------------- |
| 50 | * Helper macro to jump to the given handler if the board revision |
| 51 | * matches. |
| 52 | * Expects the Juno board revision in x0. |
| 53 | * -------------------------------------------------------------------- |
| 54 | */ |
| 55 | .macro jump_to_handler _revision, _handler |
| 56 | cmp r0, #\_revision |
| 57 | beq \_handler |
| 58 | .endm |
| 59 | |
| 60 | /* -------------------------------------------------------------------- |
| 61 | * Helper macro that reads the part number of the current CPU and jumps |
| 62 | * to the given label if it matches the CPU MIDR provided. |
| 63 | * |
| 64 | * Clobbers r0. |
| 65 | * -------------------------------------------------------------------- |
| 66 | */ |
| 67 | .macro jump_if_cpu_midr _cpu_midr, _label |
| 68 | ldcopr r0, MIDR |
| 69 | ubfx r0, r0, #MIDR_PN_SHIFT, #12 |
| 70 | ldr r1, =((\_cpu_midr >> MIDR_PN_SHIFT) & MIDR_PN_MASK) |
| 71 | cmp r0, r1 |
| 72 | beq \_label |
| 73 | .endm |
| 74 | |
| 75 | /* -------------------------------------------------------------------- |
| 76 | * Platform reset handler for Juno R0. |
| 77 | * |
| 78 | * Juno R0 has the following topology: |
| 79 | * - Quad core Cortex-A53 processor cluster; |
| 80 | * - Dual core Cortex-A57 processor cluster. |
| 81 | * |
| 82 | * This handler does the following: |
| 83 | * - Implement workaround for defect id 831273 by enabling an event |
| 84 | * stream every 65536 cycles. |
| 85 | * - Set the L2 Data RAM latency to 2 (i.e. 3 cycles) for Cortex-A57 |
| 86 | * - Set the L2 Tag RAM latency to 2 (i.e. 3 cycles) for Cortex-A57 |
| 87 | * -------------------------------------------------------------------- |
| 88 | */ |
| 89 | func JUNO_HANDLER(0) |
| 90 | /* -------------------------------------------------------------------- |
| 91 | * Enable the event stream every 65536 cycles |
| 92 | * -------------------------------------------------------------------- |
| 93 | */ |
| 94 | mov r0, #(0xf << EVNTI_SHIFT) |
| 95 | orr r0, r0, #EVNTEN_BIT |
| 96 | stcopr r0, CNTKCTL |
| 97 | |
| 98 | /* -------------------------------------------------------------------- |
| 99 | * Nothing else to do on Cortex-A53. |
| 100 | * -------------------------------------------------------------------- |
| 101 | */ |
| 102 | jump_if_cpu_midr CORTEX_A53_MIDR, 1f |
| 103 | |
| 104 | /* -------------------------------------------------------------------- |
| 105 | * Cortex-A57 specific settings |
| 106 | * -------------------------------------------------------------------- |
| 107 | */ |
| 108 | mov r0, #((L2_DATA_RAM_LATENCY_3_CYCLES << L2CTLR_DATA_RAM_LATENCY_SHIFT) | \ |
| 109 | (L2_TAG_RAM_LATENCY_3_CYCLES << L2CTLR_TAG_RAM_LATENCY_SHIFT)) |
| 110 | stcopr r0, L2CTLR |
| 111 | 1: |
| 112 | isb |
| 113 | bx lr |
| 114 | endfunc JUNO_HANDLER(0) |
| 115 | |
| 116 | /* -------------------------------------------------------------------- |
| 117 | * Platform reset handler for Juno R1. |
| 118 | * |
| 119 | * Juno R1 has the following topology: |
| 120 | * - Quad core Cortex-A53 processor cluster; |
| 121 | * - Dual core Cortex-A57 processor cluster. |
| 122 | * |
| 123 | * This handler does the following: |
| 124 | * - Set the L2 Data RAM latency to 2 (i.e. 3 cycles) for Cortex-A57 |
| 125 | * |
| 126 | * Note that: |
| 127 | * - The default value for the L2 Tag RAM latency for Cortex-A57 is |
| 128 | * suitable. |
| 129 | * - Defect #831273 doesn't affect Juno R1. |
| 130 | * -------------------------------------------------------------------- |
| 131 | */ |
| 132 | func JUNO_HANDLER(1) |
| 133 | /* -------------------------------------------------------------------- |
| 134 | * Nothing to do on Cortex-A53. |
| 135 | * -------------------------------------------------------------------- |
| 136 | */ |
| 137 | jump_if_cpu_midr CORTEX_A57_MIDR, A57 |
| 138 | bx lr |
| 139 | |
| 140 | A57: |
| 141 | /* -------------------------------------------------------------------- |
| 142 | * Cortex-A57 specific settings |
| 143 | * -------------------------------------------------------------------- |
| 144 | */ |
| 145 | mov r0, #(L2_DATA_RAM_LATENCY_3_CYCLES << L2CTLR_DATA_RAM_LATENCY_SHIFT) |
| 146 | stcopr r0, L2CTLR |
| 147 | isb |
| 148 | bx lr |
| 149 | endfunc JUNO_HANDLER(1) |
| 150 | |
| 151 | /* -------------------------------------------------------------------- |
| 152 | * Platform reset handler for Juno R2. |
| 153 | * |
| 154 | * Juno R2 has the following topology: |
| 155 | * - Quad core Cortex-A53 processor cluster; |
| 156 | * - Dual core Cortex-A72 processor cluster. |
| 157 | * |
| 158 | * This handler does the following: |
| 159 | * - Set the L2 Data RAM latency to 2 (i.e. 3 cycles) for Cortex-A72 |
| 160 | * - Set the L2 Tag RAM latency to 1 (i.e. 2 cycles) for Cortex-A72 |
| 161 | * |
| 162 | * Note that: |
| 163 | * - Defect #831273 doesn't affect Juno R2. |
| 164 | * -------------------------------------------------------------------- |
| 165 | */ |
| 166 | func JUNO_HANDLER(2) |
| 167 | /* -------------------------------------------------------------------- |
| 168 | * Nothing to do on Cortex-A53. |
| 169 | * -------------------------------------------------------------------- |
| 170 | */ |
| 171 | jump_if_cpu_midr CORTEX_A72_MIDR, A72 |
| 172 | bx lr |
| 173 | |
| 174 | A72: |
| 175 | /* -------------------------------------------------------------------- |
| 176 | * Cortex-A72 specific settings |
| 177 | * -------------------------------------------------------------------- |
| 178 | */ |
| 179 | mov r0, #((L2_DATA_RAM_LATENCY_3_CYCLES << L2CTLR_DATA_RAM_LATENCY_SHIFT) | \ |
| 180 | (L2_TAG_RAM_LATENCY_2_CYCLES << L2CTLR_TAG_RAM_LATENCY_SHIFT)) |
| 181 | stcopr r0, L2CTLR |
| 182 | isb |
| 183 | bx lr |
| 184 | endfunc JUNO_HANDLER(2) |
| 185 | |
| 186 | /* -------------------------------------------------------------------- |
| 187 | * void plat_reset_handler(void); |
| 188 | * |
| 189 | * Determine the Juno board revision and call the appropriate reset |
| 190 | * handler. |
| 191 | * -------------------------------------------------------------------- |
| 192 | */ |
| 193 | func plat_reset_handler |
| 194 | /* Read the V2M SYS_ID register */ |
| 195 | ldr r0, =(V2M_SYSREGS_BASE + V2M_SYS_ID) |
| 196 | ldr r1, [r0] |
| 197 | /* Extract board revision from the SYS_ID */ |
| 198 | ubfx r0, r1, #V2M_SYS_ID_REV_SHIFT, #4 |
| 199 | |
| 200 | JUMP_TO_HANDLER_IF_JUNO_R(0) |
| 201 | JUMP_TO_HANDLER_IF_JUNO_R(1) |
| 202 | JUMP_TO_HANDLER_IF_JUNO_R(2) |
| 203 | |
| 204 | /* Board revision is not supported */ |
| 205 | no_ret plat_panic_handler |
| 206 | |
| 207 | endfunc plat_reset_handler |
| 208 | |
| 209 | /* ----------------------------------------------------- |
| 210 | * unsigned int plat_arm_calc_core_pos(u_register_t mpidr) |
| 211 | * Helper function to calculate the core position. |
| 212 | * ----------------------------------------------------- |
| 213 | */ |
| 214 | func plat_arm_calc_core_pos |
| 215 | b css_calc_core_pos_swap_cluster |
| 216 | endfunc plat_arm_calc_core_pos |