| Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | #include <arch.h> |
| 31 | #include <asm_macros.S> |
| 32 | #include <assert_macros.S> |
| 33 | #include <cortex_a53.h> |
| 34 | #include <cpu_macros.S> |
| 35 | #include <debug.h> |
| 36 | |
| 37 | /* --------------------------------------------- |
| 38 | * Disable intra-cluster coherency |
| 39 | * --------------------------------------------- |
| 40 | */ |
| 41 | func cortex_a53_disable_smp |
| 42 | ldcopr16 r0, r1, CPUECTLR |
| 43 | bic64_imm r0, r1, CPUECTLR_SMP_BIT |
| 44 | stcopr16 r0, r1, CPUECTLR |
| 45 | isb |
| 46 | dsb sy |
| 47 | bx lr |
| 48 | endfunc cortex_a53_disable_smp |
| 49 | |
| 50 | /* ------------------------------------------------- |
| 51 | * The CPU Ops reset function for Cortex-A53. |
| 52 | * ------------------------------------------------- |
| 53 | */ |
| 54 | func cortex_a53_reset_func |
| 55 | /* --------------------------------------------- |
| 56 | * Enable the SMP bit. |
| 57 | * --------------------------------------------- |
| 58 | */ |
| 59 | ldcopr16 r0, r1, CPUECTLR |
| 60 | orr64_imm r0, r1, CPUECTLR_SMP_BIT |
| 61 | stcopr16 r0, r1, CPUECTLR |
| 62 | isb |
| 63 | bx lr |
| 64 | endfunc cortex_a53_reset_func |
| 65 | |
| 66 | /* ---------------------------------------------------- |
| 67 | * The CPU Ops core power down function for Cortex-A53. |
| 68 | * ---------------------------------------------------- |
| 69 | */ |
| 70 | func cortex_a53_core_pwr_dwn |
| 71 | push {r12, lr} |
| 72 | |
| 73 | /* Assert if cache is enabled */ |
| 74 | #if ASM_ASSERTION |
| 75 | ldcopr r0, SCTLR |
| 76 | tst r0, #SCTLR_C_BIT |
| 77 | ASM_ASSERT(eq) |
| 78 | #endif |
| 79 | |
| 80 | /* --------------------------------------------- |
| 81 | * Flush L1 caches. |
| 82 | * --------------------------------------------- |
| 83 | */ |
| 84 | mov r0, #DC_OP_CISW |
| 85 | bl dcsw_op_level1 |
| 86 | |
| 87 | /* --------------------------------------------- |
| 88 | * Come out of intra cluster coherency |
| 89 | * --------------------------------------------- |
| 90 | */ |
| 91 | pop {r12, lr} |
| 92 | b cortex_a53_disable_smp |
| 93 | endfunc cortex_a53_core_pwr_dwn |
| 94 | |
| 95 | /* ------------------------------------------------------- |
| 96 | * The CPU Ops cluster power down function for Cortex-A53. |
| 97 | * Clobbers: r0-r3 |
| 98 | * ------------------------------------------------------- |
| 99 | */ |
| 100 | func cortex_a53_cluster_pwr_dwn |
| 101 | push {r12, lr} |
| 102 | |
| 103 | /* Assert if cache is enabled */ |
| 104 | #if ASM_ASSERTION |
| 105 | ldcopr r0, SCTLR |
| 106 | tst r0, #SCTLR_C_BIT |
| 107 | ASM_ASSERT(eq) |
| 108 | #endif |
| 109 | |
| 110 | /* --------------------------------------------- |
| 111 | * Flush L1 caches. |
| 112 | * --------------------------------------------- |
| 113 | */ |
| 114 | mov r0, #DC_OP_CISW |
| 115 | bl dcsw_op_level1 |
| 116 | |
| 117 | /* --------------------------------------------- |
| 118 | * Disable the optional ACP. |
| 119 | * --------------------------------------------- |
| 120 | */ |
| 121 | bl plat_disable_acp |
| 122 | |
| 123 | /* --------------------------------------------- |
| 124 | * Flush L2 caches. |
| 125 | * --------------------------------------------- |
| 126 | */ |
| 127 | mov r0, #DC_OP_CISW |
| 128 | bl dcsw_op_level2 |
| 129 | |
| 130 | /* --------------------------------------------- |
| 131 | * Come out of intra cluster coherency |
| 132 | * --------------------------------------------- |
| 133 | */ |
| 134 | pop {r12, lr} |
| 135 | b cortex_a53_disable_smp |
| 136 | endfunc cortex_a53_cluster_pwr_dwn |
| 137 | |
| 138 | declare_cpu_ops cortex_a53, CORTEX_A53_MIDR, \ |
| 139 | cortex_a53_reset_func, \ |
| 140 | cortex_a53_core_pwr_dwn, \ |
| 141 | cortex_a53_cluster_pwr_dwn |