| Konstantin Porotchkin | f69ec58 | 2018-06-07 18:31:14 +0300 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2018 Marvell International Ltd. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | * https://spdx.org/licenses |
| 6 | */ |
| 7 | |
| 8 | #include <asm_macros.S> |
| 9 | #include <platform_def.h> |
| 10 | #include <marvell_pm.h> |
| 11 | |
| 12 | .globl plat_secondary_cold_boot_setup |
| 13 | .globl plat_get_my_entrypoint |
| 14 | .globl plat_is_my_cpu_primary |
| 15 | .globl plat_reset_handler |
| 16 | |
| 17 | /* ----------------------------------------------------- |
| 18 | * void plat_secondary_cold_boot_setup (void); |
| 19 | * |
| 20 | * This function performs any platform specific actions |
| 21 | * needed for a secondary cpu after a cold reset. Right |
| 22 | * now this is a stub function. |
| 23 | * ----------------------------------------------------- |
| 24 | */ |
| 25 | func plat_secondary_cold_boot_setup |
| 26 | mov x0, #0 |
| 27 | ret |
| 28 | endfunc plat_secondary_cold_boot_setup |
| 29 | |
| 30 | /* --------------------------------------------------------------------- |
| 31 | * unsigned long plat_get_my_entrypoint (void); |
| 32 | * |
| 33 | * Main job of this routine is to distinguish |
| 34 | * between a cold and warm boot |
| 35 | * For a cold boot, return 0. |
| 36 | * For a warm boot, read the mailbox and return the address it contains. |
| 37 | * |
| 38 | * --------------------------------------------------------------------- |
| 39 | */ |
| 40 | func plat_get_my_entrypoint |
| 41 | /* Read first word and compare it with magic num */ |
| 42 | mov_imm x0, PLAT_MARVELL_MAILBOX_BASE |
| 43 | ldr x1, [x0] |
| 44 | mov_imm x2, MVEBU_MAILBOX_MAGIC_NUM |
| 45 | cmp x1, x2 |
| 46 | beq warm_boot /* If compare failed, return 0, i.e. cold boot */ |
| 47 | mov x0, #0 |
| 48 | ret |
| 49 | warm_boot: |
| 50 | mov_imm x1, MBOX_IDX_SEC_ADDR /* Get the jump address */ |
| 51 | subs x1, x1, #1 |
| 52 | mov x2, #(MBOX_IDX_SEC_ADDR * 8) |
| 53 | lsl x3, x2, x1 |
| 54 | add x0, x0, x3 |
| 55 | ldr x0, [x0] |
| 56 | ret |
| 57 | endfunc plat_get_my_entrypoint |
| 58 | |
| 59 | /* ----------------------------------------------------- |
| 60 | * unsigned int plat_is_my_cpu_primary (void); |
| 61 | * |
| 62 | * Find out whether the current cpu is the primary |
| 63 | * cpu. |
| 64 | * ----------------------------------------------------- |
| 65 | */ |
| 66 | func plat_is_my_cpu_primary |
| 67 | mrs x0, mpidr_el1 |
| 68 | and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) |
| 69 | cmp x0, #MVEBU_PRIMARY_CPU |
| 70 | cset w0, eq |
| 71 | ret |
| 72 | endfunc plat_is_my_cpu_primary |
| 73 | |
| 74 | /* ----------------------------------------------------- |
| 75 | * void plat_reset_handler (void); |
| 76 | * |
| 77 | * Platform specific configuration right after cpu is |
| 78 | * is our of reset. |
| 79 | * |
| 80 | * The plat_reset_handler can clobber x0 - x18, x30. |
| 81 | * ----------------------------------------------------- |
| 82 | */ |
| 83 | func plat_reset_handler |
| 84 | /* |
| 85 | * Note: the configurations below should be done before MMU, |
| 86 | * I Cache and L2are enabled. |
| 87 | * The reset handler is executed right after reset |
| 88 | * and before Caches are enabled. |
| 89 | */ |
| 90 | |
| 91 | /* Enable L1/L2 ECC and Parity */ |
| 92 | mrs x5, s3_1_c11_c0_2 /* L2 Ctrl */ |
| 93 | orr x5, x5, #(1 << 21) /* Enable L1/L2 cache ECC & Parity */ |
| 94 | msr s3_1_c11_c0_2, x5 /* L2 Ctrl */ |
| 95 | |
| 96 | #if LLC_ENABLE |
| 97 | /* |
| 98 | * Enable L2 UniqueClean evictions |
| 99 | * Note: this configuration assumes that LLC is configured |
| 100 | * in exclusive mode. |
| 101 | * Later on in the code this assumption will be validated |
| 102 | */ |
| 103 | mrs x5, s3_1_c15_c0_0 /* L2 Ctrl */ |
| 104 | orr x5, x5, #(1 << 14) /* Enable UniqueClean evictions with data */ |
| 105 | msr s3_1_c15_c0_0, x5 /* L2 Ctrl */ |
| 106 | #endif |
| 107 | |
| 108 | /* Instruction Barrier to allow msr command completion */ |
| 109 | isb |
| 110 | |
| 111 | ret |
| 112 | endfunc plat_reset_handler |