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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Dan Handleye83b0ca2014-01-14 18:17:09 +00002 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <stdio.h>
32#include <string.h>
33#include <assert.h>
34#include <arch_helpers.h>
35#include <console.h>
36#include <platform.h>
37#include <bl_common.h>
38#include <bl31.h>
39#include <bakery_lock.h>
40#include <cci400.h>
41#include <gic.h>
42#include <fvp_pwrc.h>
43/* Only included for error codes */
44#include <psci.h>
45
46/*******************************************************************************
47 * FVP handler called when an affinity instance is about to be turned on. The
48 * level and mpidr determine the affinity instance.
49 ******************************************************************************/
50int fvp_affinst_on(unsigned long mpidr,
51 unsigned long sec_entrypoint,
52 unsigned long ns_entrypoint,
53 unsigned int afflvl,
54 unsigned int state)
55{
56 int rc = PSCI_E_SUCCESS;
57 unsigned long linear_id;
58 mailbox *fvp_mboxes;
59 unsigned int psysr;
60
Achin Gupta4f6ad662013-10-25 09:08:21 +010061 /*
62 * It's possible to turn on only affinity level 0 i.e. a cpu
63 * on the FVP. Ignore any other affinity level.
64 */
65 if (afflvl != MPIDR_AFFLVL0)
66 goto exit;
67
68 /*
69 * Ensure that we do not cancel an inflight power off request
70 * for the target cpu. That would leave it in a zombie wfi.
71 * Wait for it to power off, program the jump address for the
72 * target cpu and then program the power controller to turn
73 * that cpu on
74 */
75 do {
76 psysr = fvp_pwrc_read_psysr(mpidr);
77 } while (psysr & PSYSR_AFF_L0);
78
79 linear_id = platform_get_core_pos(mpidr);
80 fvp_mboxes = (mailbox *) (TZDRAM_BASE + MBOX_OFF);
81 fvp_mboxes[linear_id].value = sec_entrypoint;
82 flush_dcache_range((unsigned long) &fvp_mboxes[linear_id],
83 sizeof(unsigned long));
84
85 fvp_pwrc_write_pponr(mpidr);
86
87exit:
88 return rc;
89}
90
91/*******************************************************************************
92 * FVP handler called when an affinity instance is about to be turned off. The
93 * level and mpidr determine the affinity instance. The 'state' arg. allows the
94 * platform to decide whether the cluster is being turned off and take apt
95 * actions.
96 *
97 * CAUTION: This function is called with coherent stacks so that caches can be
98 * turned off, flushed and coherency disabled. There is no guarantee that caches
99 * will remain turned on across calls to this function as each affinity level is
100 * dealt with. So do not write & read global variables across calls. It will be
101 * wise to do flush a write to the global to prevent unpredictable results.
102 ******************************************************************************/
103int fvp_affinst_off(unsigned long mpidr,
104 unsigned int afflvl,
105 unsigned int state)
106{
107 int rc = PSCI_E_SUCCESS;
108 unsigned int gicc_base, ectlr;
Harry Liebel30affd52013-10-30 17:41:48 +0000109 unsigned long cpu_setup, cci_setup;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100110
111 switch (afflvl) {
112 case MPIDR_AFFLVL1:
113 if (state == PSCI_STATE_OFF) {
114 /*
115 * Disable coherency if this cluster is to be
116 * turned off
117 */
Harry Liebel30affd52013-10-30 17:41:48 +0000118 cci_setup = platform_get_cfgvar(CONFIG_HAS_CCI);
119 if (cci_setup) {
120 cci_disable_coherency(mpidr);
121 }
Achin Gupta4f6ad662013-10-25 09:08:21 +0100122
123 /*
124 * Program the power controller to turn the
125 * cluster off
126 */
127 fvp_pwrc_write_pcoffr(mpidr);
128
129 }
130 break;
131
132 case MPIDR_AFFLVL0:
133 if (state == PSCI_STATE_OFF) {
134
135 /*
136 * Take this cpu out of intra-cluster coherency if
137 * the FVP flavour supports the SMP bit.
138 */
139 cpu_setup = platform_get_cfgvar(CONFIG_CPU_SETUP);
140 if (cpu_setup) {
141 ectlr = read_cpuectlr();
142 ectlr &= ~CPUECTLR_SMP_BIT;
143 write_cpuectlr(ectlr);
144 }
145
146 /*
147 * Prevent interrupts from spuriously waking up
148 * this cpu
149 */
150 gicc_base = platform_get_cfgvar(CONFIG_GICC_ADDR);
151 gic_cpuif_deactivate(gicc_base);
152
153 /*
154 * Program the power controller to power this
155 * cpu off
156 */
157 fvp_pwrc_write_ppoffr(mpidr);
158 }
159 break;
160
161 default:
162 assert(0);
163 }
164
165 return rc;
166}
167
168/*******************************************************************************
169 * FVP handler called when an affinity instance is about to be suspended. The
170 * level and mpidr determine the affinity instance. The 'state' arg. allows the
171 * platform to decide whether the cluster is being turned off and take apt
172 * actions.
173 *
174 * CAUTION: This function is called with coherent stacks so that caches can be
175 * turned off, flushed and coherency disabled. There is no guarantee that caches
176 * will remain turned on across calls to this function as each affinity level is
177 * dealt with. So do not write & read global variables across calls. It will be
178 * wise to do flush a write to the global to prevent unpredictable results.
179 ******************************************************************************/
180int fvp_affinst_suspend(unsigned long mpidr,
181 unsigned long sec_entrypoint,
182 unsigned long ns_entrypoint,
183 unsigned int afflvl,
184 unsigned int state)
185{
186 int rc = PSCI_E_SUCCESS;
187 unsigned int gicc_base, ectlr;
Harry Liebel30affd52013-10-30 17:41:48 +0000188 unsigned long cpu_setup, cci_setup, linear_id;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100189 mailbox *fvp_mboxes;
190
Achin Gupta4f6ad662013-10-25 09:08:21 +0100191 switch (afflvl) {
192 case MPIDR_AFFLVL1:
193 if (state == PSCI_STATE_OFF) {
194 /*
195 * Disable coherency if this cluster is to be
196 * turned off
197 */
Harry Liebel30affd52013-10-30 17:41:48 +0000198 cci_setup = platform_get_cfgvar(CONFIG_HAS_CCI);
199 if (cci_setup) {
200 cci_disable_coherency(mpidr);
201 }
Achin Gupta4f6ad662013-10-25 09:08:21 +0100202
203 /*
204 * Program the power controller to turn the
205 * cluster off
206 */
207 fvp_pwrc_write_pcoffr(mpidr);
208
209 }
210 break;
211
212 case MPIDR_AFFLVL0:
213 if (state == PSCI_STATE_OFF) {
214 /*
215 * Take this cpu out of intra-cluster coherency if
216 * the FVP flavour supports the SMP bit.
217 */
218 cpu_setup = platform_get_cfgvar(CONFIG_CPU_SETUP);
219 if (cpu_setup) {
220 ectlr = read_cpuectlr();
221 ectlr &= ~CPUECTLR_SMP_BIT;
222 write_cpuectlr(ectlr);
223 }
224
225 /* Program the jump address for the target cpu */
226 linear_id = platform_get_core_pos(mpidr);
227 fvp_mboxes = (mailbox *) (TZDRAM_BASE + MBOX_OFF);
228 fvp_mboxes[linear_id].value = sec_entrypoint;
229 flush_dcache_range((unsigned long) &fvp_mboxes[linear_id],
230 sizeof(unsigned long));
231
232 /*
233 * Prevent interrupts from spuriously waking up
234 * this cpu
235 */
236 gicc_base = platform_get_cfgvar(CONFIG_GICC_ADDR);
237 gic_cpuif_deactivate(gicc_base);
238
239 /*
240 * Program the power controller to power this
241 * cpu off and enable wakeup interrupts.
242 */
Achin Guptab127cdb2013-11-12 16:40:00 +0000243 fvp_pwrc_set_wen(mpidr);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100244 fvp_pwrc_write_ppoffr(mpidr);
245 }
246 break;
247
248 default:
249 assert(0);
250 }
251
Achin Gupta4f6ad662013-10-25 09:08:21 +0100252 return rc;
253}
254
255/*******************************************************************************
256 * FVP handler called when an affinity instance has just been powered on after
257 * being turned off earlier. The level and mpidr determine the affinity
258 * instance. The 'state' arg. allows the platform to decide whether the cluster
259 * was turned off prior to wakeup and do what's necessary to setup it up
260 * correctly.
261 ******************************************************************************/
262int fvp_affinst_on_finish(unsigned long mpidr,
263 unsigned int afflvl,
264 unsigned int state)
265{
266 int rc = PSCI_E_SUCCESS;
Harry Liebel30affd52013-10-30 17:41:48 +0000267 unsigned long linear_id, cpu_setup, cci_setup;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100268 mailbox *fvp_mboxes;
269 unsigned int gicd_base, gicc_base, reg_val, ectlr;
270
271 switch (afflvl) {
272
273 case MPIDR_AFFLVL1:
274 /* Enable coherency if this cluster was off */
Harry Liebel30affd52013-10-30 17:41:48 +0000275 if (state == PSCI_STATE_OFF) {
Achin Guptab2187ab2014-01-17 16:52:29 +0000276
277 /*
278 * This CPU might have woken up whilst the
279 * cluster was attempting to power down. In
280 * this case the FVP power controller will
281 * have a pending cluster power off request
282 * which needs to be cleared by writing to the
283 * PPONR register. This prevents the power
284 * controller from interpreting a subsequent
285 * entry of this cpu into a simple wfi as a
286 * power down request.
287 */
288 fvp_pwrc_write_pponr(mpidr);
289
Harry Liebel30affd52013-10-30 17:41:48 +0000290 cci_setup = platform_get_cfgvar(CONFIG_HAS_CCI);
291 if (cci_setup) {
292 cci_enable_coherency(mpidr);
293 }
294 }
Achin Gupta4f6ad662013-10-25 09:08:21 +0100295 break;
296
297 case MPIDR_AFFLVL0:
298 /*
299 * Ignore the state passed for a cpu. It could only have
300 * been off if we are here.
301 */
302
303 /*
304 * Turn on intra-cluster coherency if the FVP flavour supports
305 * it.
306 */
307 cpu_setup = platform_get_cfgvar(CONFIG_CPU_SETUP);
308 if (cpu_setup) {
309 ectlr = read_cpuectlr();
310 ectlr |= CPUECTLR_SMP_BIT;
311 write_cpuectlr(ectlr);
312 }
313
Achin Guptab127cdb2013-11-12 16:40:00 +0000314 /*
315 * Clear PWKUPR.WEN bit to ensure interrupts do not interfere
316 * with a cpu power down unless the bit is set again
317 */
318 fvp_pwrc_clr_wen(mpidr);
319
Achin Gupta4f6ad662013-10-25 09:08:21 +0100320 /* Zero the jump address in the mailbox for this cpu */
321 fvp_mboxes = (mailbox *) (TZDRAM_BASE + MBOX_OFF);
322 linear_id = platform_get_core_pos(mpidr);
323 fvp_mboxes[linear_id].value = 0;
324 flush_dcache_range((unsigned long) &fvp_mboxes[linear_id],
325 sizeof(unsigned long));
326
327 gicd_base = platform_get_cfgvar(CONFIG_GICD_ADDR);
328 gicc_base = platform_get_cfgvar(CONFIG_GICC_ADDR);
329
330 /* Enable the gic cpu interface */
331 gic_cpuif_setup(gicc_base);
332
333 /* TODO: This setup is needed only after a cold boot */
334 gic_pcpu_distif_setup(gicd_base);
335
336 /* Allow access to the System counter timer module */
337 reg_val = (1 << CNTACR_RPCT_SHIFT) | (1 << CNTACR_RVCT_SHIFT);
338 reg_val |= (1 << CNTACR_RFRQ_SHIFT) | (1 << CNTACR_RVOFF_SHIFT);
339 reg_val |= (1 << CNTACR_RWVT_SHIFT) | (1 << CNTACR_RWPT_SHIFT);
340 mmio_write_32(SYS_TIMCTL_BASE + CNTACR_BASE(0), reg_val);
341 mmio_write_32(SYS_TIMCTL_BASE + CNTACR_BASE(1), reg_val);
342
343 reg_val = (1 << CNTNSAR_NS_SHIFT(0)) |
344 (1 << CNTNSAR_NS_SHIFT(1));
345 mmio_write_32(SYS_TIMCTL_BASE + CNTNSAR, reg_val);
346
347 break;
348
349 default:
350 assert(0);
351 }
352
353 return rc;
354}
355
356/*******************************************************************************
357 * FVP handler called when an affinity instance has just been powered on after
358 * having been suspended earlier. The level and mpidr determine the affinity
359 * instance.
360 * TODO: At the moment we reuse the on finisher and reinitialize the secure
361 * context. Need to implement a separate suspend finisher.
362 ******************************************************************************/
363int fvp_affinst_suspend_finish(unsigned long mpidr,
364 unsigned int afflvl,
365 unsigned int state)
366{
367 return fvp_affinst_on_finish(mpidr, afflvl, state);
368}
369
370
371/*******************************************************************************
372 * Export the platform handlers to enable psci to invoke them
373 ******************************************************************************/
374static plat_pm_ops fvp_plat_pm_ops = {
375 0,
376 fvp_affinst_on,
377 fvp_affinst_off,
378 fvp_affinst_suspend,
379 fvp_affinst_on_finish,
380 fvp_affinst_suspend_finish,
381};
382
383/*******************************************************************************
384 * Export the platform specific power ops & initialize the fvp power controller
385 ******************************************************************************/
386int platform_setup_pm(plat_pm_ops **plat_ops)
387{
388 *plat_ops = &fvp_plat_pm_ops;
389 return 0;
390}