Achin Gupta | a0cd989 | 2014-02-09 13:30:38 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #include <string.h> |
| 32 | #include <assert.h> |
| 33 | #include <arch_helpers.h> |
| 34 | #include <platform.h> |
| 35 | #include <bl_common.h> |
| 36 | |
| 37 | /******************************************************************************* |
| 38 | * TODO: Check page table alignment to avoid space wastage |
| 39 | ******************************************************************************/ |
| 40 | |
| 41 | /******************************************************************************* |
| 42 | * Level 1 translation tables need 4 entries for the 4GB address space accessib- |
| 43 | * le by the secure firmware. Input address space will be restricted using the |
| 44 | * T0SZ settings in the TCR. |
| 45 | ******************************************************************************/ |
| 46 | static unsigned long l1_xlation_table[NUM_GB_IN_4GB] |
| 47 | __attribute__ ((aligned((NUM_GB_IN_4GB) << 3))); |
| 48 | |
| 49 | /******************************************************************************* |
| 50 | * Level 2 translation tables describe the first & second gb of the address |
| 51 | * space needed to address secure peripherals e.g. trusted ROM and RAM. |
| 52 | ******************************************************************************/ |
| 53 | static unsigned long l2_xlation_table[NUM_L2_PAGETABLES][NUM_2MB_IN_GB] |
| 54 | __attribute__ ((aligned(NUM_2MB_IN_GB << 3), |
| 55 | section("xlat_table"))); |
| 56 | |
| 57 | /******************************************************************************* |
| 58 | * Level 3 translation tables (2 sets) describe the trusted & non-trusted RAM |
| 59 | * regions at a granularity of 4K. |
| 60 | ******************************************************************************/ |
| 61 | static unsigned long l3_xlation_table[NUM_L3_PAGETABLES][NUM_4K_IN_2MB] |
| 62 | __attribute__ ((aligned(NUM_4K_IN_2MB << 3), |
| 63 | section("xlat_table"))); |
| 64 | |
| 65 | /******************************************************************************* |
| 66 | * Create page tables as per the platform memory map. Certain aspects of page |
| 67 | * talble creating have been abstracted in the above routines. This can be impr- |
| 68 | * oved further. |
| 69 | * TODO: Move the page table setup helpers into the arch or lib directory |
| 70 | *******************************************************************************/ |
| 71 | unsigned long fill_xlation_tables(meminfo *tzram_layout, |
| 72 | unsigned long ro_start, |
| 73 | unsigned long ro_limit, |
| 74 | unsigned long coh_start, |
| 75 | unsigned long coh_limit) |
| 76 | { |
| 77 | unsigned long l2_desc, l3_desc; |
| 78 | unsigned long *xt_addr = 0, *pt_addr, off = 0; |
| 79 | unsigned long trom_start_index, trom_end_index; |
| 80 | unsigned long tzram_start_index, tzram_end_index; |
| 81 | unsigned long flash0_start_index, flash0_end_index; |
| 82 | unsigned long flash1_start_index, flash1_end_index; |
| 83 | unsigned long vram_start_index, vram_end_index; |
| 84 | unsigned long nsram_start_index, nsram_end_index; |
| 85 | unsigned long tdram_start_index, tdram_end_index; |
| 86 | unsigned long dram_start_index, dram_end_index; |
| 87 | unsigned long dev0_start_index, dev0_end_index; |
| 88 | unsigned long dev1_start_index, dev1_end_index; |
| 89 | unsigned int idx; |
| 90 | |
| 91 | /***************************************************************** |
| 92 | * LEVEL1 PAGETABLE SETUP |
| 93 | * |
| 94 | * Find the start and end indices of the memory peripherals in the |
| 95 | * first level pagetables. These are the main areas we care about. |
| 96 | * Also bump the end index by one if its equal to the start to |
| 97 | * allow for regions which lie completely in a GB. |
| 98 | *****************************************************************/ |
| 99 | trom_start_index = ONE_GB_INDEX(TZROM_BASE); |
| 100 | dev0_start_index = ONE_GB_INDEX(TZRNG_BASE); |
| 101 | dram_start_index = ONE_GB_INDEX(DRAM_BASE); |
| 102 | dram_end_index = ONE_GB_INDEX(DRAM_BASE + DRAM_SIZE); |
| 103 | |
| 104 | if (dram_end_index == dram_start_index) |
| 105 | dram_end_index++; |
| 106 | |
| 107 | /* |
| 108 | * Fill up the level1 translation table first |
| 109 | */ |
| 110 | for (idx = 0; idx < NUM_GB_IN_4GB; idx++) { |
| 111 | |
| 112 | /* |
| 113 | * Fill up the entry for the TZROM. This will cover |
| 114 | * everything in the first GB. |
| 115 | */ |
| 116 | if (idx == trom_start_index) { |
| 117 | xt_addr = &l2_xlation_table[GB1_L2_PAGETABLE][0]; |
| 118 | l1_xlation_table[idx] = create_table_desc(xt_addr); |
| 119 | continue; |
| 120 | } |
| 121 | |
| 122 | /* |
| 123 | * Mark the second gb as device |
| 124 | */ |
| 125 | if (idx == dev0_start_index) { |
| 126 | xt_addr = &l2_xlation_table[GB2_L2_PAGETABLE][0]; |
| 127 | l1_xlation_table[idx] = create_table_desc(xt_addr); |
| 128 | continue; |
| 129 | } |
| 130 | |
| 131 | /* |
| 132 | * Fill up the block entry for the DRAM with Normal |
| 133 | * inner-WBWA outer-WBWA non-transient attributes. |
| 134 | * This will cover 2-4GB. Note that the acesses are |
| 135 | * marked as non-secure. |
| 136 | */ |
| 137 | if ((idx >= dram_start_index) && (idx < dram_end_index)) { |
| 138 | l1_xlation_table[idx] = create_rwmem_block(idx, LEVEL1, |
| 139 | NS); |
| 140 | continue; |
| 141 | } |
| 142 | |
| 143 | assert(0); |
| 144 | } |
| 145 | |
| 146 | |
| 147 | /***************************************************************** |
| 148 | * LEVEL2 PAGETABLE SETUP |
| 149 | * |
| 150 | * Find the start and end indices of the memory & peripherals in the |
| 151 | * second level pagetables. |
| 152 | ******************************************************************/ |
| 153 | |
| 154 | /* Initializations for the 1st GB */ |
| 155 | trom_start_index = TWO_MB_INDEX(TZROM_BASE); |
| 156 | trom_end_index = TWO_MB_INDEX(TZROM_BASE + TZROM_SIZE); |
| 157 | if (trom_end_index == trom_start_index) |
| 158 | trom_end_index++; |
| 159 | |
| 160 | tdram_start_index = TWO_MB_INDEX(TZDRAM_BASE); |
| 161 | tdram_end_index = TWO_MB_INDEX(TZDRAM_BASE + TZDRAM_SIZE); |
| 162 | if (tdram_end_index == tdram_start_index) |
| 163 | tdram_end_index++; |
| 164 | |
| 165 | flash0_start_index = TWO_MB_INDEX(FLASH0_BASE); |
| 166 | flash0_end_index = TWO_MB_INDEX(FLASH0_BASE + TZROM_SIZE); |
| 167 | if (flash0_end_index == flash0_start_index) |
| 168 | flash0_end_index++; |
| 169 | |
| 170 | flash1_start_index = TWO_MB_INDEX(FLASH1_BASE); |
| 171 | flash1_end_index = TWO_MB_INDEX(FLASH1_BASE + FLASH1_SIZE); |
| 172 | if (flash1_end_index == flash1_start_index) |
| 173 | flash1_end_index++; |
| 174 | |
| 175 | vram_start_index = TWO_MB_INDEX(VRAM_BASE); |
| 176 | vram_end_index = TWO_MB_INDEX(VRAM_BASE + VRAM_SIZE); |
| 177 | if (vram_end_index == vram_start_index) |
| 178 | vram_end_index++; |
| 179 | |
| 180 | dev0_start_index = TWO_MB_INDEX(DEVICE0_BASE); |
| 181 | dev0_end_index = TWO_MB_INDEX(DEVICE0_BASE + DEVICE0_SIZE); |
| 182 | if (dev0_end_index == dev0_start_index) |
| 183 | dev0_end_index++; |
| 184 | |
| 185 | dev1_start_index = TWO_MB_INDEX(DEVICE1_BASE); |
| 186 | dev1_end_index = TWO_MB_INDEX(DEVICE1_BASE + DEVICE1_SIZE); |
| 187 | if (dev1_end_index == dev1_start_index) |
| 188 | dev1_end_index++; |
| 189 | |
| 190 | /* Since the size is < 2M this is a single index */ |
| 191 | tzram_start_index = TWO_MB_INDEX(tzram_layout->total_base); |
| 192 | nsram_start_index = TWO_MB_INDEX(NSRAM_BASE); |
| 193 | |
| 194 | /* |
| 195 | * Fill up the level2 translation table for the first GB next |
| 196 | */ |
| 197 | for (idx = 0; idx < NUM_2MB_IN_GB; idx++) { |
| 198 | |
| 199 | l2_desc = INVALID_DESC; |
| 200 | xt_addr = &l2_xlation_table[GB1_L2_PAGETABLE][idx]; |
| 201 | |
| 202 | /* Block entries for 64M of trusted Boot ROM */ |
| 203 | if ((idx >= trom_start_index) && (idx < trom_end_index)) |
| 204 | l2_desc = create_romem_block(idx, LEVEL2, 0); |
| 205 | |
| 206 | /* Single L3 page table entry for 256K of TZRAM */ |
| 207 | if (idx == tzram_start_index) { |
| 208 | pt_addr = &l3_xlation_table[TZRAM_PAGETABLE][0]; |
| 209 | l2_desc = create_table_desc(pt_addr); |
| 210 | } |
| 211 | |
| 212 | /* Block entries for 32M of trusted DRAM */ |
| 213 | if ((idx >= tdram_start_index) && (idx <= tdram_end_index)) |
| 214 | l2_desc = create_rwmem_block(idx, LEVEL2, 0); |
| 215 | |
| 216 | /* Block entries for 64M of aliased trusted Boot ROM */ |
| 217 | if ((idx >= flash0_start_index) && (idx < flash0_end_index)) |
| 218 | l2_desc = create_romem_block(idx, LEVEL2, 0); |
| 219 | |
| 220 | /* Block entries for 64M of flash1 */ |
| 221 | if ((idx >= flash1_start_index) && (idx < flash1_end_index)) |
| 222 | l2_desc = create_romem_block(idx, LEVEL2, 0); |
| 223 | |
| 224 | /* Block entries for 32M of VRAM */ |
| 225 | if ((idx >= vram_start_index) && (idx < vram_end_index)) |
| 226 | l2_desc = create_rwmem_block(idx, LEVEL2, 0); |
| 227 | |
| 228 | /* Block entries for all the devices in the first gb */ |
| 229 | if ((idx >= dev0_start_index) && (idx < dev0_end_index)) |
| 230 | l2_desc = create_device_block(idx, LEVEL2, 0); |
| 231 | |
| 232 | /* Block entries for all the devices in the first gb */ |
| 233 | if ((idx >= dev1_start_index) && (idx < dev1_end_index)) |
| 234 | l2_desc = create_device_block(idx, LEVEL2, 0); |
| 235 | |
| 236 | /* Single L3 page table entry for 64K of NSRAM */ |
| 237 | if (idx == nsram_start_index) { |
| 238 | pt_addr = &l3_xlation_table[NSRAM_PAGETABLE][0]; |
| 239 | l2_desc = create_table_desc(pt_addr); |
| 240 | } |
| 241 | |
| 242 | *xt_addr = l2_desc; |
| 243 | } |
| 244 | |
| 245 | |
| 246 | /* |
| 247 | * Initializations for the 2nd GB. Mark everything as device |
| 248 | * for the time being as the memory map is not final. Each |
| 249 | * index will need to be offset'ed to allow absolute values |
| 250 | */ |
| 251 | off = NUM_2MB_IN_GB; |
| 252 | for (idx = off; idx < (NUM_2MB_IN_GB + off); idx++) { |
| 253 | l2_desc = create_device_block(idx, LEVEL2, 0); |
| 254 | xt_addr = &l2_xlation_table[GB2_L2_PAGETABLE][idx - off]; |
| 255 | *xt_addr = l2_desc; |
| 256 | } |
| 257 | |
| 258 | |
| 259 | /***************************************************************** |
| 260 | * LEVEL3 PAGETABLE SETUP |
| 261 | *****************************************************************/ |
| 262 | |
| 263 | /* Fill up the level3 pagetable for the trusted SRAM. */ |
| 264 | tzram_start_index = FOUR_KB_INDEX(tzram_layout->total_base); |
| 265 | tzram_end_index = FOUR_KB_INDEX(tzram_layout->total_base + |
| 266 | tzram_layout->total_size); |
| 267 | if (tzram_end_index == tzram_start_index) |
| 268 | tzram_end_index++; |
| 269 | |
| 270 | /* Reusing trom* to mark RO memory. */ |
| 271 | trom_start_index = FOUR_KB_INDEX(ro_start); |
| 272 | trom_end_index = FOUR_KB_INDEX(ro_limit); |
| 273 | if (trom_end_index == trom_start_index) |
| 274 | trom_end_index++; |
| 275 | |
| 276 | /* Reusing dev* to mark coherent device memory. */ |
| 277 | dev0_start_index = FOUR_KB_INDEX(coh_start); |
| 278 | dev0_end_index = FOUR_KB_INDEX(coh_limit); |
| 279 | if (dev0_end_index == dev0_start_index) |
| 280 | dev0_end_index++; |
| 281 | |
| 282 | |
| 283 | /* Each index will need to be offset'ed to allow absolute values */ |
| 284 | off = FOUR_KB_INDEX(TZRAM_BASE); |
| 285 | for (idx = off; idx < (NUM_4K_IN_2MB + off); idx++) { |
| 286 | |
| 287 | l3_desc = INVALID_DESC; |
| 288 | xt_addr = &l3_xlation_table[TZRAM_PAGETABLE][idx - off]; |
| 289 | |
| 290 | if (idx >= tzram_start_index && idx < tzram_end_index) |
| 291 | l3_desc = create_rwmem_block(idx, LEVEL3, 0); |
| 292 | |
| 293 | if (idx >= trom_start_index && idx < trom_end_index) |
| 294 | l3_desc = create_romem_block(idx, LEVEL3, 0); |
| 295 | |
| 296 | if (idx >= dev0_start_index && idx < dev0_end_index) |
| 297 | l3_desc = create_device_block(idx, LEVEL3, 0); |
| 298 | |
| 299 | *xt_addr = l3_desc; |
| 300 | } |
| 301 | |
| 302 | /* Fill up the level3 pagetable for the non-trusted SRAM. */ |
| 303 | nsram_start_index = FOUR_KB_INDEX(NSRAM_BASE); |
| 304 | nsram_end_index = FOUR_KB_INDEX(NSRAM_BASE + NSRAM_SIZE); |
| 305 | if (nsram_end_index == nsram_start_index) |
| 306 | nsram_end_index++; |
| 307 | |
| 308 | /* Each index will need to be offset'ed to allow absolute values */ |
| 309 | off = FOUR_KB_INDEX(NSRAM_BASE); |
| 310 | for (idx = off; idx < (NUM_4K_IN_2MB + off); idx++) { |
| 311 | |
| 312 | l3_desc = INVALID_DESC; |
| 313 | xt_addr = &l3_xlation_table[NSRAM_PAGETABLE][idx - off]; |
| 314 | |
| 315 | if (idx >= nsram_start_index && idx < nsram_end_index) |
| 316 | l3_desc = create_rwmem_block(idx, LEVEL3, NS); |
| 317 | |
| 318 | *xt_addr = l3_desc; |
| 319 | } |
| 320 | |
| 321 | return (unsigned long) l1_xlation_table; |
| 322 | } |