Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 1 | /* |
Dan Handley | e83b0ca | 2014-01-14 18:17:09 +0000 | [diff] [blame] | 2 | * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #include <arch.h> |
| 32 | #include <platform.h> |
| 33 | #include <fvp_pwrc.h> |
| 34 | #include <gic.h> |
| 35 | |
| 36 | .globl platform_get_entrypoint |
| 37 | .globl platform_cold_boot_init |
| 38 | .globl plat_secondary_cold_boot_setup |
| 39 | |
| 40 | |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 41 | .section .text, "ax"; .align 3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 42 | |
| 43 | |
| 44 | .macro platform_choose_gicmmap param1, param2, x_tmp, w_tmp, res |
| 45 | ldr \x_tmp, =VE_SYSREGS_BASE + V2M_SYS_ID |
| 46 | ldr \w_tmp, [\x_tmp] |
| 47 | ubfx \w_tmp, \w_tmp, #SYS_ID_BLD_SHIFT, #SYS_ID_BLD_LENGTH |
| 48 | cmp \w_tmp, #BLD_GIC_VE_MMAP |
| 49 | csel \res, \param1, \param2, eq |
| 50 | .endm |
| 51 | |
| 52 | /* ----------------------------------------------------- |
| 53 | * void plat_secondary_cold_boot_setup (void); |
| 54 | * |
| 55 | * This function performs any platform specific actions |
| 56 | * needed for a secondary cpu after a cold reset e.g |
| 57 | * mark the cpu's presence, mechanism to place it in a |
| 58 | * holding pen etc. |
| 59 | * TODO: Should we read the PSYS register to make sure |
| 60 | * that the request has gone through. |
| 61 | * ----------------------------------------------------- |
| 62 | */ |
Jeenu Viswambharan | 3a4cae0 | 2014-01-16 17:30:39 +0000 | [diff] [blame] | 63 | plat_secondary_cold_boot_setup: ; .type plat_secondary_cold_boot_setup, %function |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 64 | bl read_mpidr |
| 65 | mov x19, x0 |
| 66 | bl platform_get_core_pos |
| 67 | mov x20, x0 |
| 68 | |
| 69 | /* --------------------------------------------- |
| 70 | * Mark this cpu as being present. This is a |
| 71 | * SO write. This array will be read using |
| 72 | * normal memory so invalidate any prefetched |
| 73 | * stale copies first. |
| 74 | * --------------------------------------------- |
| 75 | */ |
| 76 | ldr x1, =TZDRAM_BASE |
| 77 | mov x0, #AFFMAP_OFF |
| 78 | add x1, x0, x1 |
| 79 | mov x2, #PLATFORM_CACHE_LINE_SIZE |
| 80 | mul x2, x2, x20 |
| 81 | add x0, x1, x2 |
| 82 | bl dcivac |
| 83 | str x19, [x1, x2] |
| 84 | |
| 85 | /* --------------------------------------------- |
| 86 | * Power down this cpu. |
| 87 | * TODO: Do we need to worry about powering the |
| 88 | * cluster down as well here. That will need |
| 89 | * locks which we won't have unless an elf- |
| 90 | * loader zeroes out the zi section. |
| 91 | * --------------------------------------------- |
| 92 | */ |
| 93 | ldr x1, =PWRC_BASE |
| 94 | str w19, [x1, #PPOFFR_OFF] |
| 95 | |
| 96 | /* --------------------------------------------- |
| 97 | * Deactivate the gic cpu interface as well |
| 98 | * --------------------------------------------- |
| 99 | */ |
| 100 | ldr x0, =VE_GICC_BASE |
| 101 | ldr x1, =BASE_GICC_BASE |
| 102 | platform_choose_gicmmap x0, x1, x2, w2, x1 |
| 103 | mov w0, #(IRQ_BYP_DIS_GRP1 | FIQ_BYP_DIS_GRP1) |
| 104 | orr w0, w0, #(IRQ_BYP_DIS_GRP0 | FIQ_BYP_DIS_GRP0) |
| 105 | str w0, [x1, #GICC_CTLR] |
| 106 | |
| 107 | /* --------------------------------------------- |
| 108 | * There is no sane reason to come out of this |
| 109 | * wfi so panic if we do. This cpu will be pow- |
| 110 | * ered on and reset by the cpu_on pm api |
| 111 | * --------------------------------------------- |
| 112 | */ |
| 113 | dsb sy |
| 114 | wfi |
| 115 | cb_panic: |
| 116 | b cb_panic |
| 117 | |
| 118 | |
| 119 | /* ----------------------------------------------------- |
| 120 | * void platform_get_entrypoint (unsigned int mpid); |
| 121 | * |
| 122 | * Main job of this routine is to distinguish between |
| 123 | * a cold and warm boot. |
| 124 | * On a cold boot the secondaries first wait for the |
| 125 | * platform to be initialized after which they are |
| 126 | * hotplugged in. The primary proceeds to perform the |
| 127 | * platform initialization. |
| 128 | * On a warm boot, each cpu jumps to the address in its |
| 129 | * mailbox. |
| 130 | * |
| 131 | * TODO: Not a good idea to save lr in a temp reg |
| 132 | * TODO: PSYSR is a common register and should be |
| 133 | * accessed using locks. Since its not possible |
| 134 | * to use locks immediately after a cold reset |
| 135 | * we are relying on the fact that after a cold |
| 136 | * reset all cpus will read the same WK field |
| 137 | * ----------------------------------------------------- |
| 138 | */ |
Jeenu Viswambharan | 3a4cae0 | 2014-01-16 17:30:39 +0000 | [diff] [blame] | 139 | platform_get_entrypoint: ; .type platform_get_entrypoint, %function |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 140 | mov x9, x30 // lr |
| 141 | mov x2, x0 |
| 142 | ldr x1, =PWRC_BASE |
| 143 | str w2, [x1, #PSYSR_OFF] |
| 144 | ldr w2, [x1, #PSYSR_OFF] |
| 145 | ubfx w2, w2, #PSYSR_WK_SHIFT, #PSYSR_WK_MASK |
| 146 | cbnz w2, warm_reset |
| 147 | mov x0, x2 |
| 148 | b exit |
| 149 | warm_reset: |
| 150 | /* --------------------------------------------- |
| 151 | * A per-cpu mailbox is maintained in the tru- |
| 152 | * sted DRAM. Its flushed out of the caches |
| 153 | * after every update using normal memory so |
| 154 | * its safe to read it here with SO attributes |
| 155 | * --------------------------------------------- |
| 156 | */ |
| 157 | ldr x10, =TZDRAM_BASE + MBOX_OFF |
| 158 | bl platform_get_core_pos |
| 159 | lsl x0, x0, #CACHE_WRITEBACK_SHIFT |
| 160 | ldr x0, [x10, x0] |
| 161 | cbz x0, _panic |
| 162 | exit: |
| 163 | ret x9 |
| 164 | _panic: b _panic |
| 165 | |
| 166 | |
| 167 | /* ----------------------------------------------------- |
| 168 | * void platform_mem_init (void); |
| 169 | * |
| 170 | * Zero out the mailbox registers in the TZDRAM. The |
| 171 | * mmu is turned off right now and only the primary can |
| 172 | * ever execute this code. Secondaries will read the |
| 173 | * mailboxes using SO accesses. In short, BL31 will |
| 174 | * update the mailboxes after mapping the tzdram as |
| 175 | * normal memory. It will flush its copy after update. |
| 176 | * BL1 will always read the mailboxes with the MMU off |
| 177 | * ----------------------------------------------------- |
| 178 | */ |
Jeenu Viswambharan | 3a4cae0 | 2014-01-16 17:30:39 +0000 | [diff] [blame] | 179 | platform_mem_init: ; .type platform_mem_init, %function |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 180 | ldr x0, =TZDRAM_BASE + MBOX_OFF |
| 181 | stp xzr, xzr, [x0, #0] |
| 182 | stp xzr, xzr, [x0, #0x10] |
| 183 | stp xzr, xzr, [x0, #0x20] |
| 184 | stp xzr, xzr, [x0, #0x30] |
| 185 | ret |
| 186 | |
| 187 | |
| 188 | /* ----------------------------------------------------- |
| 189 | * void platform_cold_boot_init (bl1_main function); |
| 190 | * |
| 191 | * Routine called only by the primary cpu after a cold |
| 192 | * boot to perform early platform initialization |
| 193 | * ----------------------------------------------------- |
| 194 | */ |
Jeenu Viswambharan | 3a4cae0 | 2014-01-16 17:30:39 +0000 | [diff] [blame] | 195 | platform_cold_boot_init: ; .type platform_cold_boot_init, %function |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 196 | mov x20, x0 |
| 197 | bl platform_mem_init |
| 198 | bl read_mpidr |
| 199 | mov x19, x0 |
| 200 | |
| 201 | /* --------------------------------------------- |
| 202 | * Give ourselves a small coherent stack to |
| 203 | * ease the pain of initializing the MMU and |
| 204 | * CCI in assembler |
| 205 | * --------------------------------------------- |
| 206 | */ |
| 207 | bl platform_set_coherent_stack |
| 208 | |
| 209 | /* --------------------------------------------- |
| 210 | * Mark this cpu as being present. This is a |
| 211 | * SO write. Invalidate any stale copies out of |
| 212 | * paranoia as there is no one else around. |
| 213 | * --------------------------------------------- |
| 214 | */ |
| 215 | mov x0, x19 |
| 216 | bl platform_get_core_pos |
| 217 | mov x21, x0 |
| 218 | |
| 219 | ldr x1, =TZDRAM_BASE |
| 220 | mov x0, #AFFMAP_OFF |
| 221 | add x1, x0, x1 |
| 222 | mov x2, #PLATFORM_CACHE_LINE_SIZE |
| 223 | mul x2, x2, x21 |
| 224 | add x0, x1, x2 |
| 225 | bl dcivac |
| 226 | str x19, [x1, x2] |
| 227 | |
| 228 | /* --------------------------------------------- |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 229 | * Architectural init. can be generic e.g. |
| 230 | * enabling stack alignment and platform spec- |
| 231 | * ific e.g. MMU & page table setup as per the |
| 232 | * platform memory map. Perform the latter here |
| 233 | * and the former in bl1_main. |
| 234 | * --------------------------------------------- |
| 235 | */ |
| 236 | bl bl1_early_platform_setup |
| 237 | bl bl1_plat_arch_setup |
| 238 | |
| 239 | /* --------------------------------------------- |
| 240 | * Give ourselves a stack allocated in Normal |
| 241 | * -IS-WBWA memory |
| 242 | * --------------------------------------------- |
| 243 | */ |
| 244 | mov x0, x19 |
| 245 | bl platform_set_stack |
| 246 | |
| 247 | /* --------------------------------------------- |
| 248 | * Jump to the main function. Returning from it |
| 249 | * is a terminal error. |
| 250 | * --------------------------------------------- |
| 251 | */ |
| 252 | blr x20 |
| 253 | |
| 254 | cb_init_panic: |
| 255 | b cb_init_panic |