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Soren Brinkmann76fcae32016-03-06 20:16:27 -08001/*
Jeenu Viswambharan9bde1302017-09-29 11:15:18 +01002 * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved.
Soren Brinkmann76fcae32016-03-06 20:16:27 -08003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Soren Brinkmann76fcae32016-03-06 20:16:27 -08005 */
6
7#ifndef __PLATFORM_DEF_H__
8#define __PLATFORM_DEF_H__
9
10#include <arch.h>
Jeenu Viswambharan9bde1302017-09-29 11:15:18 +010011#include <gic_common.h>
12#include <interrupt_props.h>
Soren Brinkmann76fcae32016-03-06 20:16:27 -080013#include "../zynqmp_def.h"
14
15/*******************************************************************************
16 * Generic platform constants
17 ******************************************************************************/
18
19/* Size of cacheable stacks */
20#define PLATFORM_STACK_SIZE 0x440
21
22#define PLATFORM_CORE_COUNT 4
23#define PLAT_NUM_POWER_DOMAINS 5
24#define PLAT_MAX_PWR_LVL 1
25#define PLAT_MAX_RET_STATE 1
26#define PLAT_MAX_OFF_STATE 2
27
28/*******************************************************************************
29 * BL31 specific defines.
30 ******************************************************************************/
Soren Brinkmann76fcae32016-03-06 20:16:27 -080031/*
32 * Put BL31 at the top of the Trusted SRAM (just below the shared memory, if
33 * present). BL31_BASE is calculated using the current BL31 debug size plus a
34 * little space for growth.
35 */
Soren Brinkmann4a9ca042016-04-14 10:27:00 -070036#ifndef ZYNQMP_ATF_MEM_BASE
Soren Brinkmann802ba1d2016-07-15 06:23:37 -070037# define BL31_BASE 0xfffea000
Soren Brinkmann4a9ca042016-04-14 10:27:00 -070038# define BL31_LIMIT 0xffffffff
Soren Brinkmann76fcae32016-03-06 20:16:27 -080039#else
Soren Brinkmann4a9ca042016-04-14 10:27:00 -070040# define BL31_BASE (ZYNQMP_ATF_MEM_BASE)
41# define BL31_LIMIT (ZYNQMP_ATF_MEM_BASE + ZYNQMP_ATF_MEM_SIZE - 1)
42# ifdef ZYNQMP_ATF_MEM_PROGBITS_SIZE
43# define BL31_PROGBITS_LIMIT (ZYNQMP_ATF_MEM_BASE + ZYNQMP_ATF_MEM_PROGBITS_SIZE - 1)
44# endif
Soren Brinkmann76fcae32016-03-06 20:16:27 -080045#endif
46
47/*******************************************************************************
48 * BL32 specific defines.
49 ******************************************************************************/
Soren Brinkmann4a9ca042016-04-14 10:27:00 -070050#ifndef ZYNQMP_BL32_MEM_BASE
51# define BL32_BASE 0x60000000
52# define BL32_LIMIT 0x7fffffff
Soren Brinkmann76fcae32016-03-06 20:16:27 -080053#else
Soren Brinkmann4a9ca042016-04-14 10:27:00 -070054# define BL32_BASE (ZYNQMP_BL32_MEM_BASE)
55# define BL32_LIMIT (ZYNQMP_BL32_MEM_BASE + ZYNQMP_BL32_MEM_SIZE - 1)
Soren Brinkmann76fcae32016-03-06 20:16:27 -080056#endif
57
Soren Brinkmann4a9ca042016-04-14 10:27:00 -070058/*******************************************************************************
59 * BL33 specific defines.
60 ******************************************************************************/
61#ifndef PRELOADED_BL33_BASE
62# define PLAT_ARM_NS_IMAGE_OFFSET 0x8000000
63#else
64# define PLAT_ARM_NS_IMAGE_OFFSET PRELOADED_BL33_BASE
65#endif
66
67/*******************************************************************************
68 * TSP specific defines.
69 ******************************************************************************/
70#define TSP_SEC_MEM_BASE BL32_BASE
71#define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE + 1)
72
73/* ID of the secure physical generic timer interrupt used by the TSP */
Soren Brinkmann76fcae32016-03-06 20:16:27 -080074#define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER
75
76/*******************************************************************************
77 * Platform specific page table and MMU setup constants
78 ******************************************************************************/
Soren Brinkmann6a9e03e2017-01-06 11:07:00 -080079#define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 32)
80#define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 32)
Soren Brinkmann6d1ba582016-07-08 14:45:14 -070081#define MAX_MMAP_REGIONS 7
Soren Brinkmann7ac746c2016-07-25 10:33:53 -070082#define MAX_XLAT_TABLES 5
Soren Brinkmann76fcae32016-03-06 20:16:27 -080083
84#define CACHE_WRITEBACK_SHIFT 6
85#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
86
87#define PLAT_ARM_GICD_BASE BASE_GICD_BASE
88#define PLAT_ARM_GICC_BASE BASE_GICC_BASE
89/*
Jeenu Viswambharan9bde1302017-09-29 11:15:18 +010090 * Define properties of Group 1 Secure and Group 0 interrupts as per GICv3
Soren Brinkmann76fcae32016-03-06 20:16:27 -080091 * terminology. On a GICv2 system or mode, the lists will be merged and treated
92 * as Group 0 interrupts.
93 */
Jeenu Viswambharan9bde1302017-09-29 11:15:18 +010094#define PLAT_ARM_G1S_IRQ_PROPS(grp) \
95 INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \
96 GIC_INTR_CFG_LEVEL), \
97 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \
98 GIC_INTR_CFG_EDGE), \
99 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \
100 GIC_INTR_CFG_EDGE), \
101 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \
102 GIC_INTR_CFG_EDGE), \
103 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \
104 GIC_INTR_CFG_EDGE), \
105 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \
106 GIC_INTR_CFG_EDGE), \
107 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \
108 GIC_INTR_CFG_EDGE), \
109 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \
110 GIC_INTR_CFG_EDGE), \
111 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \
112 GIC_INTR_CFG_EDGE)
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800113
Jeenu Viswambharan9bde1302017-09-29 11:15:18 +0100114#define PLAT_ARM_G0_IRQ_PROPS(grp)
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800115
116#endif /* __PLATFORM_DEF_H__ */