blob: 030eea723cc29d57b534f181515477eea9c51b6d [file] [log] [blame]
Soby Mathew12012dd2015-10-26 14:01:53 +00001/*
Jeenu Viswambharanb1e957e2017-09-22 08:32:09 +01002 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
Soby Mathew12012dd2015-10-26 14:01:53 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Soby Mathew12012dd2015-10-26 14:01:53 +00005 */
6#include <arch_helpers.h>
7#include <assert.h>
8#include <bl_common.h>
9#include <cassert.h>
10#include <gic_common.h>
11#include <gicv3.h>
12#include <interrupt_mgmt.h>
13#include <platform.h>
14
Masahiro Yamada441bfdd2016-12-25 23:36:24 +090015#ifdef IMAGE_BL31
Soby Mathew12012dd2015-10-26 14:01:53 +000016
17/*
18 * The following platform GIC functions are weakly defined. They
19 * provide typical implementations that may be re-used by multiple
20 * platforms but may also be overridden by a platform if required.
21 */
22#pragma weak plat_ic_get_pending_interrupt_id
23#pragma weak plat_ic_get_pending_interrupt_type
24#pragma weak plat_ic_acknowledge_interrupt
25#pragma weak plat_ic_get_interrupt_type
26#pragma weak plat_ic_end_of_interrupt
27#pragma weak plat_interrupt_type_to_line
28
Jeenu Viswambharanb1e957e2017-09-22 08:32:09 +010029#pragma weak plat_ic_get_running_priority
Jeenu Viswambharan522a4652017-09-22 08:32:09 +010030#pragma weak plat_ic_is_spi
31#pragma weak plat_ic_is_ppi
32#pragma weak plat_ic_is_sgi
Jeenu Viswambharan24e70292017-09-22 08:32:09 +010033#pragma weak plat_ic_get_interrupt_active
Jeenu Viswambharan0fcdfff2017-09-22 08:32:09 +010034#pragma weak plat_ic_enable_interrupt
35#pragma weak plat_ic_disable_interrupt
Jeenu Viswambharan447b89d2017-09-22 08:32:09 +010036#pragma weak plat_ic_set_interrupt_priority
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +010037#pragma weak plat_ic_set_interrupt_type
Jeenu Viswambharanab14e9b2017-09-22 08:32:09 +010038#pragma weak plat_ic_raise_el3_sgi
Jeenu Viswambharandce70b32017-09-22 08:32:09 +010039#pragma weak plat_ic_set_spi_routing
Jeenu Viswambharaneb1c12c2017-09-22 08:32:09 +010040#pragma weak plat_ic_set_interrupt_pending
41#pragma weak plat_ic_clear_interrupt_pending
Jeenu Viswambharanb1e957e2017-09-22 08:32:09 +010042
Soby Mathew12012dd2015-10-26 14:01:53 +000043CASSERT((INTR_TYPE_S_EL1 == INTR_GROUP1S) &&
44 (INTR_TYPE_NS == INTR_GROUP1NS) &&
45 (INTR_TYPE_EL3 == INTR_GROUP0), assert_interrupt_type_mismatch);
46
47/*
48 * This function returns the highest priority pending interrupt at
49 * the Interrupt controller
50 */
51uint32_t plat_ic_get_pending_interrupt_id(void)
52{
53 unsigned int irqnr;
54
55 assert(IS_IN_EL3());
56 irqnr = gicv3_get_pending_interrupt_id();
57 return (gicv3_is_intr_id_special_identifier(irqnr)) ?
58 INTR_ID_UNAVAILABLE : irqnr;
59}
60
61/*
62 * This function returns the type of the highest priority pending interrupt
63 * at the Interrupt controller. In the case of GICv3, the Highest Priority
64 * Pending interrupt system register (`ICC_HPPIR0_EL1`) is read to determine
65 * the id of the pending interrupt. The type of interrupt depends upon the
66 * id value as follows.
67 * 1. id = PENDING_G1S_INTID (1020) is reported as a S-EL1 interrupt
68 * 2. id = PENDING_G1NS_INTID (1021) is reported as a Non-secure interrupt.
69 * 3. id = GIC_SPURIOUS_INTERRUPT (1023) is reported as an invalid interrupt
70 * type.
71 * 4. All other interrupt id's are reported as EL3 interrupt.
72 */
73uint32_t plat_ic_get_pending_interrupt_type(void)
74{
75 unsigned int irqnr;
76
77 assert(IS_IN_EL3());
78 irqnr = gicv3_get_pending_interrupt_type();
79
80 switch (irqnr) {
81 case PENDING_G1S_INTID:
82 return INTR_TYPE_S_EL1;
83 case PENDING_G1NS_INTID:
84 return INTR_TYPE_NS;
85 case GIC_SPURIOUS_INTERRUPT:
86 return INTR_TYPE_INVAL;
87 default:
88 return INTR_TYPE_EL3;
89 }
90}
91
92/*
93 * This function returns the highest priority pending interrupt at
94 * the Interrupt controller and indicates to the Interrupt controller
95 * that the interrupt processing has started.
96 */
97uint32_t plat_ic_acknowledge_interrupt(void)
98{
99 assert(IS_IN_EL3());
100 return gicv3_acknowledge_interrupt();
101}
102
103/*
104 * This function returns the type of the interrupt `id`, depending on how
105 * the interrupt has been configured in the interrupt controller
106 */
107uint32_t plat_ic_get_interrupt_type(uint32_t id)
108{
109 assert(IS_IN_EL3());
110 return gicv3_get_interrupt_type(id, plat_my_core_pos());
111}
112
113/*
114 * This functions is used to indicate to the interrupt controller that
115 * the processing of the interrupt corresponding to the `id` has
116 * finished.
117 */
118void plat_ic_end_of_interrupt(uint32_t id)
119{
120 assert(IS_IN_EL3());
121 gicv3_end_of_interrupt(id);
122}
123
124/*
125 * An ARM processor signals interrupt exceptions through the IRQ and FIQ pins.
126 * The interrupt controller knows which pin/line it uses to signal a type of
127 * interrupt. It lets the interrupt management framework determine for a type of
128 * interrupt and security state, which line should be used in the SCR_EL3 to
129 * control its routing to EL3. The interrupt line is represented as the bit
130 * position of the IRQ or FIQ bit in the SCR_EL3.
131 */
132uint32_t plat_interrupt_type_to_line(uint32_t type,
133 uint32_t security_state)
134{
135 assert(type == INTR_TYPE_S_EL1 ||
136 type == INTR_TYPE_EL3 ||
137 type == INTR_TYPE_NS);
138
139 assert(sec_state_is_valid(security_state));
140 assert(IS_IN_EL3());
141
142 switch (type) {
143 case INTR_TYPE_S_EL1:
144 /*
145 * The S-EL1 interrupts are signaled as IRQ in S-EL0/1 contexts
146 * and as FIQ in the NS-EL0/1/2 contexts
147 */
148 if (security_state == SECURE)
149 return __builtin_ctz(SCR_IRQ_BIT);
150 else
151 return __builtin_ctz(SCR_FIQ_BIT);
152 case INTR_TYPE_NS:
153 /*
154 * The Non secure interrupts will be signaled as FIQ in S-EL0/1
155 * contexts and as IRQ in the NS-EL0/1/2 contexts.
156 */
157 if (security_state == SECURE)
158 return __builtin_ctz(SCR_FIQ_BIT);
159 else
160 return __builtin_ctz(SCR_IRQ_BIT);
161 default:
162 assert(0);
163 /* Fall through in the release build */
164 case INTR_TYPE_EL3:
165 /*
166 * The EL3 interrupts are signaled as FIQ in both S-EL0/1 and
167 * NS-EL0/1/2 contexts
168 */
169 return __builtin_ctz(SCR_FIQ_BIT);
170 }
171}
Jeenu Viswambharanb1e957e2017-09-22 08:32:09 +0100172
173unsigned int plat_ic_get_running_priority(void)
174{
175 return gicv3_get_running_priority();
176}
177
Jeenu Viswambharan522a4652017-09-22 08:32:09 +0100178int plat_ic_is_spi(unsigned int id)
179{
180 return (id >= MIN_SPI_ID) && (id <= MAX_SPI_ID);
181}
182
183int plat_ic_is_ppi(unsigned int id)
184{
185 return (id >= MIN_PPI_ID) && (id < MIN_SPI_ID);
186}
187
188int plat_ic_is_sgi(unsigned int id)
189{
190 return (id >= MIN_SGI_ID) && (id < MIN_PPI_ID);
191}
Jeenu Viswambharan24e70292017-09-22 08:32:09 +0100192
193unsigned int plat_ic_get_interrupt_active(unsigned int id)
194{
195 return gicv3_get_interrupt_active(id, plat_my_core_pos());
196}
Jeenu Viswambharan0fcdfff2017-09-22 08:32:09 +0100197
198void plat_ic_enable_interrupt(unsigned int id)
199{
200 gicv3_enable_interrupt(id, plat_my_core_pos());
201}
202
203void plat_ic_disable_interrupt(unsigned int id)
204{
205 gicv3_disable_interrupt(id, plat_my_core_pos());
206}
Jeenu Viswambharan447b89d2017-09-22 08:32:09 +0100207
208void plat_ic_set_interrupt_priority(unsigned int id, unsigned int priority)
209{
210 gicv3_set_interrupt_priority(id, plat_my_core_pos(), priority);
211}
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +0100212
213int plat_ic_has_interrupt_type(unsigned int type)
214{
215 assert((type == INTR_TYPE_EL3) || (type == INTR_TYPE_S_EL1) ||
216 (type == INTR_TYPE_NS));
217 return 1;
218}
219
220void plat_ic_set_interrupt_type(unsigned int id, unsigned int type)
221{
222 gicv3_set_interrupt_type(id, plat_my_core_pos(), type);
223}
Jeenu Viswambharanab14e9b2017-09-22 08:32:09 +0100224
225void plat_ic_raise_el3_sgi(int sgi_num, u_register_t target)
226{
227 /* Target must be a valid MPIDR in the system */
228 assert(plat_core_pos_by_mpidr(target) >= 0);
229
230 /* Verify that this is a secure EL3 SGI */
231 assert(plat_ic_get_interrupt_type(sgi_num) == INTR_TYPE_EL3);
232
233 gicv3_raise_secure_g0_sgi(sgi_num, target);
234}
Jeenu Viswambharandce70b32017-09-22 08:32:09 +0100235
236void plat_ic_set_spi_routing(unsigned int id, unsigned int routing_mode,
237 u_register_t mpidr)
238{
239 unsigned int irm = 0;
240
241 switch (routing_mode) {
242 case INTR_ROUTING_MODE_PE:
243 assert(plat_core_pos_by_mpidr(mpidr) >= 0);
244 irm = GICV3_IRM_PE;
245 break;
246 case INTR_ROUTING_MODE_ANY:
247 irm = GICV3_IRM_ANY;
248 break;
249 default:
250 assert(0);
251 }
252
253 gicv3_set_spi_routing(id, irm, mpidr);
254}
Jeenu Viswambharaneb1c12c2017-09-22 08:32:09 +0100255
256void plat_ic_set_interrupt_pending(unsigned int id)
257{
258 /* Disallow setting SGIs pending */
259 assert(id >= MIN_PPI_ID);
260 gicv3_set_interrupt_pending(id, plat_my_core_pos());
261}
262
263void plat_ic_clear_interrupt_pending(unsigned int id)
264{
265 /* Disallow setting SGIs pending */
266 assert(id >= MIN_PPI_ID);
267 gicv3_clear_interrupt_pending(id, plat_my_core_pos());
268}
Jeenu Viswambharan62505072017-09-22 08:32:09 +0100269
270unsigned int plat_ic_set_priority_mask(unsigned int mask)
271{
272 return gicv3_set_pmr(mask);
273}
Jeenu Viswambharan055af4b2017-10-24 15:13:59 +0100274
275unsigned int plat_ic_get_interrupt_id(unsigned int raw)
276{
277 unsigned int id = (raw & INT_ID_MASK);
278
279 return (gicv3_is_intr_id_special_identifier(id) ?
280 INTR_ID_UNAVAILABLE : id);
281}
Soby Mathew12012dd2015-10-26 14:01:53 +0000282#endif
Masahiro Yamada441bfdd2016-12-25 23:36:24 +0900283#ifdef IMAGE_BL32
Soby Mathew12012dd2015-10-26 14:01:53 +0000284
285#pragma weak plat_ic_get_pending_interrupt_id
286#pragma weak plat_ic_acknowledge_interrupt
287#pragma weak plat_ic_end_of_interrupt
288
Soby Mathew0d268dc2016-07-11 14:13:56 +0100289/* In AArch32, the secure group1 interrupts are targeted to Secure PL1 */
290#ifdef AARCH32
291#define IS_IN_EL1() IS_IN_SECURE()
292#endif
293
Soby Mathew12012dd2015-10-26 14:01:53 +0000294/*
295 * This function returns the highest priority pending interrupt at
296 * the Interrupt controller
297 */
298uint32_t plat_ic_get_pending_interrupt_id(void)
299{
300 unsigned int irqnr;
301
302 assert(IS_IN_EL1());
303 irqnr = gicv3_get_pending_interrupt_id_sel1();
304 return (irqnr == GIC_SPURIOUS_INTERRUPT) ?
305 INTR_ID_UNAVAILABLE : irqnr;
306}
307
308/*
309 * This function returns the highest priority pending interrupt at
310 * the Interrupt controller and indicates to the Interrupt controller
311 * that the interrupt processing has started.
312 */
313uint32_t plat_ic_acknowledge_interrupt(void)
314{
315 assert(IS_IN_EL1());
316 return gicv3_acknowledge_interrupt_sel1();
317}
318
319/*
320 * This functions is used to indicate to the interrupt controller that
321 * the processing of the interrupt corresponding to the `id` has
322 * finished.
323 */
324void plat_ic_end_of_interrupt(uint32_t id)
325{
326 assert(IS_IN_EL1());
327 gicv3_end_of_interrupt_sel1(id);
328}
329#endif