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Soby Mathew7b754182016-07-11 14:15:27 +01001/*
Soby Mathew7d5a2e72018-01-10 15:59:31 +00002 * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
Soby Mathew7b754182016-07-11 14:15:27 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Soby Mathew7b754182016-07-11 14:15:27 +01005 */
6
7#include <plat_arm.h>
8#include "../fvp_private.h"
9
Soby Mathew7d5a2e72018-01-10 15:59:31 +000010void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1,
11 u_register_t arg2, u_register_t arg3)
Soby Mathew7b754182016-07-11 14:15:27 +010012{
Soby Mathew7d5a2e72018-01-10 15:59:31 +000013 arm_sp_min_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3);
Soby Mathew7b754182016-07-11 14:15:27 +010014
15 /* Initialize the platform config for future decision making */
16 fvp_config_setup();
17
18 /*
19 * Initialize the correct interconnect for this cluster during cold
20 * boot. No need for locks as no other CPU is active.
21 */
22 fvp_interconnect_init();
23
24 /*
25 * Enable coherency in interconnect for the primary CPU's cluster.
26 * Earlier bootloader stages might already do this (e.g. Trusted
27 * Firmware's BL1 does it) but we can't assume so. There is no harm in
28 * executing this code twice anyway.
29 * FVP PSCI code will enable coherency for other clusters.
30 */
31 fvp_interconnect_enable();
32}