Achin Gupta | 607084e | 2014-02-09 18:24:19 +0000 | [diff] [blame] | 1 | /* |
Douglas Raillard | f212965 | 2016-11-24 15:43:19 +0000 | [diff] [blame] | 2 | * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 607084e | 2014-02-09 18:24:19 +0000 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Achin Gupta | 607084e | 2014-02-09 18:24:19 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
Achin Gupta | 607084e | 2014-02-09 18:24:19 +0000 | [diff] [blame] | 7 | #include <arch_helpers.h> |
Dan Handley | 2bd4ef2 | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 8 | #include <assert.h> |
| 9 | #include <bl_common.h> |
Achin Gupta | 607084e | 2014-02-09 18:24:19 +0000 | [diff] [blame] | 10 | #include <context_mgmt.h> |
Achin Gupta | 607084e | 2014-02-09 18:24:19 +0000 | [diff] [blame] | 11 | #include <debug.h> |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 12 | #include <platform.h> |
Dan Handley | 2bd4ef2 | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 13 | #include <tsp.h> |
Dan Handley | 714a0d2 | 2014-04-09 13:13:04 +0100 | [diff] [blame] | 14 | #include "tspd_private.h" |
Achin Gupta | 607084e | 2014-02-09 18:24:19 +0000 | [diff] [blame] | 15 | |
| 16 | /******************************************************************************* |
| 17 | * The target cpu is being turned on. Allow the TSPD/TSP to perform any actions |
| 18 | * needed. Nothing at the moment. |
| 19 | ******************************************************************************/ |
Masahiro Yamada | 5ac9d96 | 2018-04-19 01:18:48 +0900 | [diff] [blame] | 20 | static void tspd_cpu_on_handler(u_register_t target_cpu) |
Achin Gupta | 607084e | 2014-02-09 18:24:19 +0000 | [diff] [blame] | 21 | { |
| 22 | } |
| 23 | |
| 24 | /******************************************************************************* |
| 25 | * This cpu is being turned off. Allow the TSPD/TSP to perform any actions |
| 26 | * needed |
| 27 | ******************************************************************************/ |
Masahiro Yamada | 5ac9d96 | 2018-04-19 01:18:48 +0900 | [diff] [blame] | 28 | static int32_t tspd_cpu_off_handler(u_register_t unused) |
Achin Gupta | 607084e | 2014-02-09 18:24:19 +0000 | [diff] [blame] | 29 | { |
| 30 | int32_t rc = 0; |
Soby Mathew | da43b66 | 2015-07-08 21:45:46 +0100 | [diff] [blame] | 31 | uint32_t linear_id = plat_my_core_pos(); |
Dan Handley | e2712bc | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 32 | tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id]; |
Achin Gupta | 607084e | 2014-02-09 18:24:19 +0000 | [diff] [blame] | 33 | |
Andrew Thoelke | 891c4ca | 2014-05-20 21:43:27 +0100 | [diff] [blame] | 34 | assert(tsp_vectors); |
Achin Gupta | 18d6eaf | 2014-05-04 18:23:26 +0100 | [diff] [blame] | 35 | assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_ON); |
Achin Gupta | 607084e | 2014-02-09 18:24:19 +0000 | [diff] [blame] | 36 | |
Douglas Raillard | f212965 | 2016-11-24 15:43:19 +0000 | [diff] [blame] | 37 | /* |
| 38 | * Abort any preempted SMC request before overwriting the SECURE |
| 39 | * context. |
| 40 | */ |
| 41 | tspd_abort_preempted_smc(tsp_ctx); |
| 42 | |
Achin Gupta | 607084e | 2014-02-09 18:24:19 +0000 | [diff] [blame] | 43 | /* Program the entry point and enter the TSP */ |
Andrew Thoelke | 891c4ca | 2014-05-20 21:43:27 +0100 | [diff] [blame] | 44 | cm_set_elr_el3(SECURE, (uint64_t) &tsp_vectors->cpu_off_entry); |
Achin Gupta | 607084e | 2014-02-09 18:24:19 +0000 | [diff] [blame] | 45 | rc = tspd_synchronous_sp_entry(tsp_ctx); |
| 46 | |
| 47 | /* |
| 48 | * Read the response from the TSP. A non-zero return means that |
| 49 | * something went wrong while communicating with the TSP. |
| 50 | */ |
| 51 | if (rc != 0) |
| 52 | panic(); |
| 53 | |
| 54 | /* |
| 55 | * Reset TSP's context for a fresh start when this cpu is turned on |
| 56 | * subsequently. |
| 57 | */ |
Achin Gupta | 18d6eaf | 2014-05-04 18:23:26 +0100 | [diff] [blame] | 58 | set_tsp_pstate(tsp_ctx->state, TSP_PSTATE_OFF); |
Achin Gupta | 607084e | 2014-02-09 18:24:19 +0000 | [diff] [blame] | 59 | |
Douglas Raillard | f212965 | 2016-11-24 15:43:19 +0000 | [diff] [blame] | 60 | return 0; |
Achin Gupta | 607084e | 2014-02-09 18:24:19 +0000 | [diff] [blame] | 61 | } |
| 62 | |
| 63 | /******************************************************************************* |
| 64 | * This cpu is being suspended. S-EL1 state must have been saved in the |
| 65 | * resident cpu (mpidr format) if it is a UP/UP migratable TSP. |
| 66 | ******************************************************************************/ |
Masahiro Yamada | 5ac9d96 | 2018-04-19 01:18:48 +0900 | [diff] [blame] | 67 | static void tspd_cpu_suspend_handler(u_register_t max_off_pwrlvl) |
Achin Gupta | 607084e | 2014-02-09 18:24:19 +0000 | [diff] [blame] | 68 | { |
| 69 | int32_t rc = 0; |
Soby Mathew | da43b66 | 2015-07-08 21:45:46 +0100 | [diff] [blame] | 70 | uint32_t linear_id = plat_my_core_pos(); |
Dan Handley | e2712bc | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 71 | tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id]; |
Achin Gupta | 607084e | 2014-02-09 18:24:19 +0000 | [diff] [blame] | 72 | |
Andrew Thoelke | 891c4ca | 2014-05-20 21:43:27 +0100 | [diff] [blame] | 73 | assert(tsp_vectors); |
Achin Gupta | 18d6eaf | 2014-05-04 18:23:26 +0100 | [diff] [blame] | 74 | assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_ON); |
Achin Gupta | 607084e | 2014-02-09 18:24:19 +0000 | [diff] [blame] | 75 | |
Douglas Raillard | f212965 | 2016-11-24 15:43:19 +0000 | [diff] [blame] | 76 | /* |
| 77 | * Abort any preempted SMC request before overwriting the SECURE |
| 78 | * context. |
| 79 | */ |
| 80 | tspd_abort_preempted_smc(tsp_ctx); |
| 81 | |
Soby Mathew | f512157 | 2014-09-30 11:19:51 +0100 | [diff] [blame] | 82 | /* Program the entry point and enter the TSP */ |
Andrew Thoelke | 891c4ca | 2014-05-20 21:43:27 +0100 | [diff] [blame] | 83 | cm_set_elr_el3(SECURE, (uint64_t) &tsp_vectors->cpu_suspend_entry); |
Achin Gupta | 607084e | 2014-02-09 18:24:19 +0000 | [diff] [blame] | 84 | rc = tspd_synchronous_sp_entry(tsp_ctx); |
| 85 | |
| 86 | /* |
| 87 | * Read the response from the TSP. A non-zero return means that |
| 88 | * something went wrong while communicating with the TSP. |
| 89 | */ |
Douglas Raillard | f212965 | 2016-11-24 15:43:19 +0000 | [diff] [blame] | 90 | if (rc) |
Achin Gupta | 607084e | 2014-02-09 18:24:19 +0000 | [diff] [blame] | 91 | panic(); |
| 92 | |
| 93 | /* Update its context to reflect the state the TSP is in */ |
Achin Gupta | 18d6eaf | 2014-05-04 18:23:26 +0100 | [diff] [blame] | 94 | set_tsp_pstate(tsp_ctx->state, TSP_PSTATE_SUSPEND); |
Achin Gupta | 607084e | 2014-02-09 18:24:19 +0000 | [diff] [blame] | 95 | } |
| 96 | |
| 97 | /******************************************************************************* |
| 98 | * This cpu has been turned on. Enter the TSP to initialise S-EL1 and other bits |
Douglas Raillard | f212965 | 2016-11-24 15:43:19 +0000 | [diff] [blame] | 99 | * before passing control back to the Secure Monitor. Entry in S-EL1 is done |
Achin Gupta | 607084e | 2014-02-09 18:24:19 +0000 | [diff] [blame] | 100 | * after initialising minimal architectural state that guarantees safe |
| 101 | * execution. |
| 102 | ******************************************************************************/ |
Masahiro Yamada | 5ac9d96 | 2018-04-19 01:18:48 +0900 | [diff] [blame] | 103 | static void tspd_cpu_on_finish_handler(u_register_t unused) |
Achin Gupta | 607084e | 2014-02-09 18:24:19 +0000 | [diff] [blame] | 104 | { |
| 105 | int32_t rc = 0; |
Soby Mathew | da43b66 | 2015-07-08 21:45:46 +0100 | [diff] [blame] | 106 | uint32_t linear_id = plat_my_core_pos(); |
Dan Handley | e2712bc | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 107 | tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id]; |
Vikram Kanigiri | 9d70f0f | 2014-07-15 16:46:43 +0100 | [diff] [blame] | 108 | entry_point_info_t tsp_on_entrypoint; |
Achin Gupta | 607084e | 2014-02-09 18:24:19 +0000 | [diff] [blame] | 109 | |
Andrew Thoelke | 891c4ca | 2014-05-20 21:43:27 +0100 | [diff] [blame] | 110 | assert(tsp_vectors); |
Achin Gupta | 18d6eaf | 2014-05-04 18:23:26 +0100 | [diff] [blame] | 111 | assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_OFF); |
Achin Gupta | 607084e | 2014-02-09 18:24:19 +0000 | [diff] [blame] | 112 | |
Vikram Kanigiri | 9d70f0f | 2014-07-15 16:46:43 +0100 | [diff] [blame] | 113 | tspd_init_tsp_ep_state(&tsp_on_entrypoint, |
Achin Gupta | 607084e | 2014-02-09 18:24:19 +0000 | [diff] [blame] | 114 | TSP_AARCH64, |
Vikram Kanigiri | 9d70f0f | 2014-07-15 16:46:43 +0100 | [diff] [blame] | 115 | (uint64_t) &tsp_vectors->cpu_on_entry, |
Achin Gupta | 607084e | 2014-02-09 18:24:19 +0000 | [diff] [blame] | 116 | tsp_ctx); |
| 117 | |
Vikram Kanigiri | 9d70f0f | 2014-07-15 16:46:43 +0100 | [diff] [blame] | 118 | /* Initialise this cpu's secure context */ |
Soby Mathew | da43b66 | 2015-07-08 21:45:46 +0100 | [diff] [blame] | 119 | cm_init_my_context(&tsp_on_entrypoint); |
Vikram Kanigiri | 9d70f0f | 2014-07-15 16:46:43 +0100 | [diff] [blame] | 120 | |
Soby Mathew | bec9851 | 2015-09-03 18:29:38 +0100 | [diff] [blame] | 121 | #if TSP_NS_INTR_ASYNC_PREEMPT |
Soby Mathew | 47903c0 | 2015-01-13 15:48:26 +0000 | [diff] [blame] | 122 | /* |
| 123 | * Disable the NS interrupt locally since it will be enabled globally |
Soby Mathew | da43b66 | 2015-07-08 21:45:46 +0100 | [diff] [blame] | 124 | * within cm_init_my_context. |
Soby Mathew | 47903c0 | 2015-01-13 15:48:26 +0000 | [diff] [blame] | 125 | */ |
| 126 | disable_intr_rm_local(INTR_TYPE_NS, SECURE); |
| 127 | #endif |
| 128 | |
Achin Gupta | 607084e | 2014-02-09 18:24:19 +0000 | [diff] [blame] | 129 | /* Enter the TSP */ |
| 130 | rc = tspd_synchronous_sp_entry(tsp_ctx); |
| 131 | |
| 132 | /* |
| 133 | * Read the response from the TSP. A non-zero return means that |
| 134 | * something went wrong while communicating with the SP. |
| 135 | */ |
| 136 | if (rc != 0) |
| 137 | panic(); |
| 138 | |
| 139 | /* Update its context to reflect the state the SP is in */ |
Achin Gupta | 18d6eaf | 2014-05-04 18:23:26 +0100 | [diff] [blame] | 140 | set_tsp_pstate(tsp_ctx->state, TSP_PSTATE_ON); |
Achin Gupta | 607084e | 2014-02-09 18:24:19 +0000 | [diff] [blame] | 141 | } |
| 142 | |
| 143 | /******************************************************************************* |
| 144 | * This cpu has resumed from suspend. The SPD saved the TSP context when it |
| 145 | * completed the preceding suspend call. Use that context to program an entry |
| 146 | * into the TSP to allow it to do any remaining book keeping |
| 147 | ******************************************************************************/ |
Masahiro Yamada | 5ac9d96 | 2018-04-19 01:18:48 +0900 | [diff] [blame] | 148 | static void tspd_cpu_suspend_finish_handler(u_register_t max_off_pwrlvl) |
Achin Gupta | 607084e | 2014-02-09 18:24:19 +0000 | [diff] [blame] | 149 | { |
| 150 | int32_t rc = 0; |
Soby Mathew | da43b66 | 2015-07-08 21:45:46 +0100 | [diff] [blame] | 151 | uint32_t linear_id = plat_my_core_pos(); |
Dan Handley | e2712bc | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 152 | tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id]; |
Achin Gupta | 607084e | 2014-02-09 18:24:19 +0000 | [diff] [blame] | 153 | |
Andrew Thoelke | 891c4ca | 2014-05-20 21:43:27 +0100 | [diff] [blame] | 154 | assert(tsp_vectors); |
Achin Gupta | 18d6eaf | 2014-05-04 18:23:26 +0100 | [diff] [blame] | 155 | assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_SUSPEND); |
Achin Gupta | 607084e | 2014-02-09 18:24:19 +0000 | [diff] [blame] | 156 | |
Achin Gupta | 9a0ff9b | 2015-09-07 20:43:27 +0100 | [diff] [blame] | 157 | /* Program the entry point, max_off_pwrlvl and enter the SP */ |
Achin Gupta | 607084e | 2014-02-09 18:24:19 +0000 | [diff] [blame] | 158 | write_ctx_reg(get_gpregs_ctx(&tsp_ctx->cpu_ctx), |
| 159 | CTX_GPREG_X0, |
Achin Gupta | 9a0ff9b | 2015-09-07 20:43:27 +0100 | [diff] [blame] | 160 | max_off_pwrlvl); |
Andrew Thoelke | 891c4ca | 2014-05-20 21:43:27 +0100 | [diff] [blame] | 161 | cm_set_elr_el3(SECURE, (uint64_t) &tsp_vectors->cpu_resume_entry); |
Achin Gupta | 607084e | 2014-02-09 18:24:19 +0000 | [diff] [blame] | 162 | rc = tspd_synchronous_sp_entry(tsp_ctx); |
| 163 | |
| 164 | /* |
| 165 | * Read the response from the TSP. A non-zero return means that |
| 166 | * something went wrong while communicating with the TSP. |
| 167 | */ |
| 168 | if (rc != 0) |
| 169 | panic(); |
| 170 | |
| 171 | /* Update its context to reflect the state the SP is in */ |
Achin Gupta | 18d6eaf | 2014-05-04 18:23:26 +0100 | [diff] [blame] | 172 | set_tsp_pstate(tsp_ctx->state, TSP_PSTATE_ON); |
Achin Gupta | 607084e | 2014-02-09 18:24:19 +0000 | [diff] [blame] | 173 | } |
| 174 | |
| 175 | /******************************************************************************* |
| 176 | * Return the type of TSP the TSPD is dealing with. Report the current resident |
| 177 | * cpu (mpidr format) if it is a UP/UP migratable TSP. |
| 178 | ******************************************************************************/ |
Masahiro Yamada | 5ac9d96 | 2018-04-19 01:18:48 +0900 | [diff] [blame] | 179 | static int32_t tspd_cpu_migrate_info(u_register_t *resident_cpu) |
Achin Gupta | 607084e | 2014-02-09 18:24:19 +0000 | [diff] [blame] | 180 | { |
| 181 | return TSP_MIGRATE_INFO; |
| 182 | } |
| 183 | |
| 184 | /******************************************************************************* |
Juan Castillo | 4dc4a47 | 2014-08-12 11:17:06 +0100 | [diff] [blame] | 185 | * System is about to be switched off. Allow the TSPD/TSP to perform |
| 186 | * any actions needed. |
| 187 | ******************************************************************************/ |
| 188 | static void tspd_system_off(void) |
| 189 | { |
Soby Mathew | da43b66 | 2015-07-08 21:45:46 +0100 | [diff] [blame] | 190 | uint32_t linear_id = plat_my_core_pos(); |
Juan Castillo | 4dc4a47 | 2014-08-12 11:17:06 +0100 | [diff] [blame] | 191 | tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id]; |
| 192 | |
| 193 | assert(tsp_vectors); |
| 194 | assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_ON); |
| 195 | |
Douglas Raillard | f212965 | 2016-11-24 15:43:19 +0000 | [diff] [blame] | 196 | /* |
| 197 | * Abort any preempted SMC request before overwriting the SECURE |
| 198 | * context. |
| 199 | */ |
| 200 | tspd_abort_preempted_smc(tsp_ctx); |
| 201 | |
Juan Castillo | 4dc4a47 | 2014-08-12 11:17:06 +0100 | [diff] [blame] | 202 | /* Program the entry point */ |
| 203 | cm_set_elr_el3(SECURE, (uint64_t) &tsp_vectors->system_off_entry); |
| 204 | |
| 205 | /* Enter the TSP. We do not care about the return value because we |
| 206 | * must continue the shutdown anyway */ |
| 207 | tspd_synchronous_sp_entry(tsp_ctx); |
| 208 | } |
| 209 | |
| 210 | /******************************************************************************* |
| 211 | * System is about to be reset. Allow the TSPD/TSP to perform |
| 212 | * any actions needed. |
| 213 | ******************************************************************************/ |
| 214 | static void tspd_system_reset(void) |
| 215 | { |
Soby Mathew | da43b66 | 2015-07-08 21:45:46 +0100 | [diff] [blame] | 216 | uint32_t linear_id = plat_my_core_pos(); |
Juan Castillo | 4dc4a47 | 2014-08-12 11:17:06 +0100 | [diff] [blame] | 217 | tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id]; |
| 218 | |
| 219 | assert(tsp_vectors); |
| 220 | assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_ON); |
| 221 | |
Douglas Raillard | f212965 | 2016-11-24 15:43:19 +0000 | [diff] [blame] | 222 | /* |
| 223 | * Abort any preempted SMC request before overwriting the SECURE |
| 224 | * context. |
| 225 | */ |
| 226 | tspd_abort_preempted_smc(tsp_ctx); |
| 227 | |
Juan Castillo | 4dc4a47 | 2014-08-12 11:17:06 +0100 | [diff] [blame] | 228 | /* Program the entry point */ |
| 229 | cm_set_elr_el3(SECURE, (uint64_t) &tsp_vectors->system_reset_entry); |
| 230 | |
Douglas Raillard | f212965 | 2016-11-24 15:43:19 +0000 | [diff] [blame] | 231 | /* |
| 232 | * Enter the TSP. We do not care about the return value because we |
| 233 | * must continue the reset anyway |
| 234 | */ |
Juan Castillo | 4dc4a47 | 2014-08-12 11:17:06 +0100 | [diff] [blame] | 235 | tspd_synchronous_sp_entry(tsp_ctx); |
| 236 | } |
| 237 | |
| 238 | /******************************************************************************* |
Achin Gupta | 607084e | 2014-02-09 18:24:19 +0000 | [diff] [blame] | 239 | * Structure populated by the TSP Dispatcher to be given a chance to perform any |
| 240 | * TSP bookkeeping before PSCI executes a power mgmt. operation. |
| 241 | ******************************************************************************/ |
Dan Handley | e2712bc | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 242 | const spd_pm_ops_t tspd_pm = { |
Juan Castillo | 4dc4a47 | 2014-08-12 11:17:06 +0100 | [diff] [blame] | 243 | .svc_on = tspd_cpu_on_handler, |
| 244 | .svc_off = tspd_cpu_off_handler, |
| 245 | .svc_suspend = tspd_cpu_suspend_handler, |
| 246 | .svc_on_finish = tspd_cpu_on_finish_handler, |
| 247 | .svc_suspend_finish = tspd_cpu_suspend_finish_handler, |
| 248 | .svc_migrate = NULL, |
| 249 | .svc_migrate_info = tspd_cpu_migrate_info, |
| 250 | .svc_system_off = tspd_system_off, |
| 251 | .svc_system_reset = tspd_system_reset |
Achin Gupta | 607084e | 2014-02-09 18:24:19 +0000 | [diff] [blame] | 252 | }; |