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Masahiro Yamada574388c2016-09-03 11:37:40 +09001/*
Antonio Nino Diaz4b32e622018-08-16 16:52:57 +01002 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
Masahiro Yamada574388c2016-09-03 11:37:40 +09003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Masahiro Yamada574388c2016-09-03 11:37:40 +09007#include <assert.h>
Antonio Nino Diaz4b32e622018-08-16 16:52:57 +01008#include <stdint.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00009
10#include <platform_def.h>
11
12#include <arch_helpers.h>
13#include <drivers/io/io_block.h>
14#include <lib/mmio.h>
15#include <lib/utils_def.h>
Masahiro Yamada574388c2016-09-03 11:37:40 +090016
17#include "uniphier.h"
18
19#define MMC_CMD_SWITCH 6
20#define MMC_CMD_SELECT_CARD 7
21#define MMC_CMD_SEND_CSD 9
22#define MMC_CMD_READ_MULTIPLE_BLOCK 18
23
24#define EXT_CSD_PART_CONF 179 /* R/W */
25
26#define MMC_RSP_PRESENT BIT(0)
27#define MMC_RSP_136 BIT(1) /* 136 bit response */
28#define MMC_RSP_CRC BIT(2) /* expect valid crc */
29#define MMC_RSP_BUSY BIT(3) /* card may send busy */
30#define MMC_RSP_OPCODE BIT(4) /* response contains opcode */
31
32#define MMC_RSP_NONE (0)
33#define MMC_RSP_R1 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)
34#define MMC_RSP_R1b (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE | \
35 MMC_RSP_BUSY)
36#define MMC_RSP_R2 (MMC_RSP_PRESENT | MMC_RSP_136 | MMC_RSP_CRC)
37#define MMC_RSP_R3 (MMC_RSP_PRESENT)
38#define MMC_RSP_R4 (MMC_RSP_PRESENT)
39#define MMC_RSP_R5 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)
40#define MMC_RSP_R6 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)
41#define MMC_RSP_R7 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)
42
43#define SDHCI_DMA_ADDRESS 0x00
44#define SDHCI_BLOCK_SIZE 0x04
45#define SDHCI_MAKE_BLKSZ(dma, blksz) ((((dma) & 0x7) << 12) | ((blksz) & 0xFFF))
46#define SDHCI_BLOCK_COUNT 0x06
47#define SDHCI_ARGUMENT 0x08
48#define SDHCI_TRANSFER_MODE 0x0C
49#define SDHCI_TRNS_DMA BIT(0)
50#define SDHCI_TRNS_BLK_CNT_EN BIT(1)
51#define SDHCI_TRNS_ACMD12 BIT(2)
52#define SDHCI_TRNS_READ BIT(4)
53#define SDHCI_TRNS_MULTI BIT(5)
54#define SDHCI_COMMAND 0x0E
55#define SDHCI_CMD_RESP_MASK 0x03
56#define SDHCI_CMD_CRC 0x08
57#define SDHCI_CMD_INDEX 0x10
58#define SDHCI_CMD_DATA 0x20
59#define SDHCI_CMD_ABORTCMD 0xC0
60#define SDHCI_CMD_RESP_NONE 0x00
61#define SDHCI_CMD_RESP_LONG 0x01
62#define SDHCI_CMD_RESP_SHORT 0x02
63#define SDHCI_CMD_RESP_SHORT_BUSY 0x03
64#define SDHCI_MAKE_CMD(c, f) ((((c) & 0xff) << 8) | ((f) & 0xff))
65#define SDHCI_RESPONSE 0x10
66#define SDHCI_HOST_CONTROL 0x28
67#define SDHCI_CTRL_DMA_MASK 0x18
68#define SDHCI_CTRL_SDMA 0x00
69#define SDHCI_BLOCK_GAP_CONTROL 0x2A
70#define SDHCI_SOFTWARE_RESET 0x2F
71#define SDHCI_RESET_CMD 0x02
72#define SDHCI_RESET_DATA 0x04
73#define SDHCI_INT_STATUS 0x30
74#define SDHCI_INT_RESPONSE BIT(0)
75#define SDHCI_INT_DATA_END BIT(1)
76#define SDHCI_INT_DMA_END BIT(3)
77#define SDHCI_INT_ERROR BIT(15)
78#define SDHCI_SIGNAL_ENABLE 0x38
79
80/* RCA assigned by Boot ROM */
81#define UNIPHIER_EMMC_RCA 0x1000
82
83struct uniphier_mmc_cmd {
84 unsigned int cmdidx;
85 unsigned int resp_type;
86 unsigned int cmdarg;
87 unsigned int is_data;
88};
89
90static int uniphier_emmc_block_addressing;
91
92static int uniphier_emmc_send_cmd(uintptr_t host_base,
93 struct uniphier_mmc_cmd *cmd)
94{
95 uint32_t mode = 0;
96 uint32_t end_bit;
97 uint32_t stat, flags, dma_addr;
98
99 mmio_write_32(host_base + SDHCI_INT_STATUS, -1);
100 mmio_write_32(host_base + SDHCI_SIGNAL_ENABLE, 0);
101 mmio_write_32(host_base + SDHCI_ARGUMENT, cmd->cmdarg);
102
103 if (cmd->is_data)
104 mode = SDHCI_TRNS_DMA | SDHCI_TRNS_BLK_CNT_EN |
105 SDHCI_TRNS_ACMD12 | SDHCI_TRNS_READ |
106 SDHCI_TRNS_MULTI;
107
108 mmio_write_16(host_base + SDHCI_TRANSFER_MODE, mode);
109
110 if (!(cmd->resp_type & MMC_RSP_PRESENT))
111 flags = SDHCI_CMD_RESP_NONE;
112 else if (cmd->resp_type & MMC_RSP_136)
113 flags = SDHCI_CMD_RESP_LONG;
114 else if (cmd->resp_type & MMC_RSP_BUSY)
115 flags = SDHCI_CMD_RESP_SHORT_BUSY;
116 else
117 flags = SDHCI_CMD_RESP_SHORT;
118
119 if (cmd->resp_type & MMC_RSP_CRC)
120 flags |= SDHCI_CMD_CRC;
121 if (cmd->resp_type & MMC_RSP_OPCODE)
122 flags |= SDHCI_CMD_INDEX;
123 if (cmd->is_data)
124 flags |= SDHCI_CMD_DATA;
125
126 if (cmd->resp_type & MMC_RSP_BUSY || cmd->is_data)
127 end_bit = SDHCI_INT_DATA_END;
128 else
129 end_bit = SDHCI_INT_RESPONSE;
130
131 mmio_write_16(host_base + SDHCI_COMMAND,
132 SDHCI_MAKE_CMD(cmd->cmdidx, flags));
133
134 do {
135 stat = mmio_read_32(host_base + SDHCI_INT_STATUS);
136 if (stat & SDHCI_INT_ERROR)
137 return -EIO;
138
139 if (stat & SDHCI_INT_DMA_END) {
140 mmio_write_32(host_base + SDHCI_INT_STATUS, stat);
141 dma_addr = mmio_read_32(host_base + SDHCI_DMA_ADDRESS);
142 mmio_write_32(host_base + SDHCI_DMA_ADDRESS, dma_addr);
143 }
144 } while (!(stat & end_bit));
145
146 return 0;
147}
148
149static int uniphier_emmc_switch_part(uintptr_t host_base, int part_num)
150{
151 struct uniphier_mmc_cmd cmd = {0};
152
153 cmd.cmdidx = MMC_CMD_SWITCH;
154 cmd.resp_type = MMC_RSP_R1b;
155 cmd.cmdarg = (EXT_CSD_PART_CONF << 16) | (part_num << 8) | (3 << 24);
156
157 return uniphier_emmc_send_cmd(host_base, &cmd);
158}
159
160static int uniphier_emmc_is_over_2gb(uintptr_t host_base)
161{
162 struct uniphier_mmc_cmd cmd = {0};
163 uint32_t csd40, csd72; /* CSD[71:40], CSD[103:72] */
164 int ret;
165
166 cmd.cmdidx = MMC_CMD_SEND_CSD;
167 cmd.resp_type = MMC_RSP_R2;
168 cmd.cmdarg = UNIPHIER_EMMC_RCA << 16;
169
170 ret = uniphier_emmc_send_cmd(host_base, &cmd);
171 if (ret)
172 return ret;
173
174 csd40 = mmio_read_32(host_base + SDHCI_RESPONSE + 4);
175 csd72 = mmio_read_32(host_base + SDHCI_RESPONSE + 8);
176
177 return !(~csd40 & 0xffc00380) && !(~csd72 & 0x3);
178}
179
180static int uniphier_emmc_load_image(uintptr_t host_base,
181 uint32_t dev_addr,
182 unsigned long load_addr,
183 uint32_t block_cnt)
184{
185 struct uniphier_mmc_cmd cmd = {0};
186 uint8_t tmp;
187
188 assert((load_addr >> 32) == 0);
189
190 mmio_write_32(host_base + SDHCI_DMA_ADDRESS, load_addr);
191 mmio_write_16(host_base + SDHCI_BLOCK_SIZE, SDHCI_MAKE_BLKSZ(7, 512));
192 mmio_write_16(host_base + SDHCI_BLOCK_COUNT, block_cnt);
193
194 tmp = mmio_read_8(host_base + SDHCI_HOST_CONTROL);
195 tmp &= ~SDHCI_CTRL_DMA_MASK;
196 tmp |= SDHCI_CTRL_SDMA;
197 mmio_write_8(host_base + SDHCI_HOST_CONTROL, tmp);
198
199 tmp = mmio_read_8(host_base + SDHCI_BLOCK_GAP_CONTROL);
200 tmp &= ~1; /* clear Stop At Block Gap Request */
201 mmio_write_8(host_base + SDHCI_BLOCK_GAP_CONTROL, tmp);
202
203 cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK;
204 cmd.resp_type = MMC_RSP_R1;
205 cmd.cmdarg = dev_addr;
206 cmd.is_data = 1;
207
208 return uniphier_emmc_send_cmd(host_base, &cmd);
209}
210
211static size_t uniphier_emmc_read(int lba, uintptr_t buf, size_t size)
212{
213 uintptr_t host_base = 0x5a000200;
214 int ret;
215
216 inv_dcache_range(buf, size);
217
218 if (!uniphier_emmc_block_addressing)
219 lba *= 512;
220
221 ret = uniphier_emmc_load_image(host_base, lba, buf, size / 512);
222
223 inv_dcache_range(buf, size);
224
225 return ret ? 0 : size;
226}
227
228static const struct io_block_dev_spec uniphier_emmc_dev_spec = {
229 .buffer = {
230 .offset = UNIPHIER_BLOCK_BUF_BASE,
231 .length = UNIPHIER_BLOCK_BUF_SIZE,
232 },
233 .ops = {
234 .read = uniphier_emmc_read,
235 },
236 .block_size = 512,
237};
238
239static int uniphier_emmc_hw_init(void)
240{
241 uintptr_t host_base = 0x5a000200;
242 struct uniphier_mmc_cmd cmd = {0};
243 int ret;
244
245 /*
246 * deselect card before SEND_CSD command.
247 * Do not check the return code. It fails, but it is OK.
248 */
249 cmd.cmdidx = MMC_CMD_SELECT_CARD;
250 cmd.resp_type = MMC_RSP_R1;
251
252 uniphier_emmc_send_cmd(host_base, &cmd); /* CMD7 (arg=0) */
253
254 /* reset CMD Line */
255 mmio_write_8(host_base + SDHCI_SOFTWARE_RESET,
256 SDHCI_RESET_CMD | SDHCI_RESET_DATA);
257 while (mmio_read_8(host_base + SDHCI_SOFTWARE_RESET))
258 ;
259
260 ret = uniphier_emmc_is_over_2gb(host_base);
261 if (ret < 0)
262 return ret;
263
264 uniphier_emmc_block_addressing = ret;
265
266 cmd.cmdarg = UNIPHIER_EMMC_RCA << 16;
267
268 /* select card again */
269 ret = uniphier_emmc_send_cmd(host_base, &cmd);
270 if (ret)
271 return ret;
272
273 /* switch to Boot Partition 1 */
274 ret = uniphier_emmc_switch_part(host_base, 1);
275 if (ret)
276 return ret;
277
278 return 0;
279}
280
281int uniphier_emmc_init(uintptr_t *block_dev_spec)
282{
283 int ret;
284
285 ret = uniphier_emmc_hw_init();
286 if (ret)
287 return ret;
288
289 *block_dev_spec = (uintptr_t)&uniphier_emmc_dev_spec;
290
291 return 0;
292}