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git01.mediatek.com / filogic / atf / 7a849804c24417022e0cf97c6024908d736ebc29 / . / plat / arm / css / sgi / sgi_bl31_setup.c
blob: 541689bc83810232c9bd2a65ec3691c0cac6cc5e [file] [log] [blame]
Nariman Poushin0ece80f2018-02-26 06:52:04 +0000[diff] [blame]1/*
Vijayenthiran Subramaniam2b4ad8d2019-09-23 19:32:32 +0530[diff] [blame]2 * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
Nariman Poushin0ece80f2018-02-26 06:52:04 +0000[diff] [blame]3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Chandni Cherukuric8ef0452018-10-04 16:32:03 +0530[diff] [blame]7#include <assert.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +0000[diff] [blame]8
Chandni Cherukuric8ef0452018-10-04 16:32:03 +0530[diff] [blame]9#include <libfdt.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +0000[diff] [blame]10
11#include <common/bl_common.h>
12#include <common/debug.h>
Antonio Nino Diaz1b0c6f12019-01-23 21:08:43 +0000[diff] [blame]13#include <drivers/arm/css/css_mhu_doorbell.h>
Antonio Nino Diazc30db5b2019-01-23 20:37:32 +0000[diff] [blame]14#include <drivers/arm/css/scmi.h>
Antonio Nino Diazbd7b7402019-01-25 14:30:04 +0000[diff] [blame]15#include <plat/arm/common/plat_arm.h>
Ambroise Vincentb237bca2019-02-13 15:58:00 +0000[diff] [blame]16#include <plat/common/platform.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +0000[diff] [blame]17
Sughosh Ganu18f513d2018-05-16 17:22:35 +0530[diff] [blame]18#include <sgi_ras.h>
Chandni Cherukuric8ef0452018-10-04 16:32:03 +0530[diff] [blame]19#include <sgi_variant.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +0000[diff] [blame]20
Chandni Cherukuric8ef0452018-10-04 16:32:03 +0530[diff] [blame]21sgi_platform_info_t sgi_plat_info;
22
Chandni Cherukuri61f3a7c2018-10-11 14:08:08 +0530[diff] [blame]23static scmi_channel_plat_info_t sgi575_scmi_plat_info = {
24 .scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE,
25 .db_reg_addr = PLAT_CSS_MHU_BASE + CSS_SCMI_MHU_DB_REG_OFF,
26 .db_preserve_mask = 0xfffffffe,
27 .db_modify_mask = 0x1,
28 .ring_doorbell = &mhu_ring_doorbell,
29};
30
Aditya Angadidf9904a2021-01-28 12:15:16 +0530[diff] [blame]31static scmi_channel_plat_info_t plat_rd_scmi_info[] = {
Vijayenthiran Subramaniamc4e68a42019-10-28 14:49:48 +0530[diff] [blame]32 {
Chandni Cherukuric8ef0452018-10-04 16:32:03 +0530[diff] [blame]33 .scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE,
34 .db_reg_addr = PLAT_CSS_MHU_BASE + SENDER_REG_SET(0),
35 .db_preserve_mask = 0xfffffffe,
36 .db_modify_mask = 0x1,
37 .ring_doorbell = &mhuv2_ring_doorbell,
Vijayenthiran Subramaniamc4e68a42019-10-28 14:49:48 +0530[diff] [blame]38 },
39 #if (CSS_SGI_CHIP_COUNT > 1)
40 {
41 .scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE +
42 CSS_SGI_REMOTE_CHIP_MEM_OFFSET(1),
43 .db_reg_addr = PLAT_CSS_MHU_BASE
44 + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(1) + SENDER_REG_SET(0),
45 .db_preserve_mask = 0xfffffffe,
46 .db_modify_mask = 0x1,
47 .ring_doorbell = &mhuv2_ring_doorbell,
48 },
49 #endif
50 #if (CSS_SGI_CHIP_COUNT > 2)
51 {
52 .scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE +
53 CSS_SGI_REMOTE_CHIP_MEM_OFFSET(2),
54 .db_reg_addr = PLAT_CSS_MHU_BASE +
55 CSS_SGI_REMOTE_CHIP_MEM_OFFSET(2) + SENDER_REG_SET(0),
56 .db_preserve_mask = 0xfffffffe,
57 .db_modify_mask = 0x1,
58 .ring_doorbell = &mhuv2_ring_doorbell,
59 },
60 #endif
61 #if (CSS_SGI_CHIP_COUNT > 3)
62 {
63 .scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE +
64 CSS_SGI_REMOTE_CHIP_MEM_OFFSET(3),
65 .db_reg_addr = PLAT_CSS_MHU_BASE +
66 CSS_SGI_REMOTE_CHIP_MEM_OFFSET(3) + SENDER_REG_SET(0),
67 .db_preserve_mask = 0xfffffffe,
68 .db_modify_mask = 0x1,
69 .ring_doorbell = &mhuv2_ring_doorbell,
70 },
71 #endif
Chandni Cherukuric8ef0452018-10-04 16:32:03 +0530[diff] [blame]72};
73
Aditya Angadi7f8837b2019-12-31 14:23:53 +0530[diff] [blame]74scmi_channel_plat_info_t *plat_css_get_scmi_info(int channel_id)
Chandni Cherukuri61f3a7c2018-10-11 14:08:08 +0530[diff] [blame]75{
Aditya Angadie6508952019-07-21 22:13:45 +0530[diff] [blame]76 if (sgi_plat_info.platform_id == RD_N1E1_EDGE_SID_VER_PART_NUM ||
Aditya Angadied339d82020-12-15 17:10:50 +0530[diff] [blame]77 sgi_plat_info.platform_id == RD_V1_SID_VER_PART_NUM ||
Aditya Angadif894b9a2021-03-20 12:15:04 +0530[diff] [blame]78 sgi_plat_info.platform_id == RD_N2_SID_VER_PART_NUM ||
79 sgi_plat_info.platform_id == RD_N2_CFG1_SID_VER_PART_NUM) {
Aditya Angadidf9904a2021-01-28 12:15:16 +0530[diff] [blame]80 if (channel_id >= ARRAY_SIZE(plat_rd_scmi_info))
Vijayenthiran Subramaniamc4e68a42019-10-28 14:49:48 +0530[diff] [blame]81 panic();
Aditya Angadidf9904a2021-01-28 12:15:16 +0530[diff] [blame]82 return &plat_rd_scmi_info[channel_id];
Vijayenthiran Subramaniamc4e68a42019-10-28 14:49:48 +0530[diff] [blame]83 }
Chandni Cherukuric8ef0452018-10-04 16:32:03 +0530[diff] [blame]84 else if (sgi_plat_info.platform_id == SGI575_SSC_VER_PART_NUM)
85 return &sgi575_scmi_plat_info;
86 else
87 panic();
Ambroise Vincentb237bca2019-02-13 15:58:00 +0000[diff] [blame]88}
Chandni Cherukuric8ef0452018-10-04 16:32:03 +0530[diff] [blame]89
Nariman Poushin0ece80f2018-02-26 06:52:04 +0000[diff] [blame]90void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
91 u_register_t arg2, u_register_t arg3)
92{
Chandni Cherukuri3aa09f72018-11-28 11:31:51 +0530[diff] [blame]93 sgi_plat_info.platform_id = plat_arm_sgi_get_platform_id();
94 sgi_plat_info.config_id = plat_arm_sgi_get_config_id();
Vijayenthiran Subramaniam8af18432019-10-22 15:46:14 +0530[diff] [blame]95 sgi_plat_info.multi_chip_mode = plat_arm_sgi_get_multi_chip_mode();
Chandni Cherukuric8ef0452018-10-04 16:32:03 +0530[diff] [blame]96
Nariman Poushin0ece80f2018-02-26 06:52:04 +0000[diff] [blame]97 arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3);
98}
Sughosh Ganu18f513d2018-05-16 17:22:35 +0530[diff] [blame]99
Vijayenthiran Subramaniam2b4ad8d2019-09-23 19:32:32 +0530[diff] [blame]100void sgi_bl31_common_platform_setup(void)
Sughosh Ganu18f513d2018-05-16 17:22:35 +0530[diff] [blame]101{
102 arm_bl31_platform_setup();
103
104#if RAS_EXTENSION
105 sgi_ras_intr_handler_setup();
106#endif
107}
Chandni Cherukurie4bf6a02018-11-14 13:43:59 +0530[diff] [blame]108
109const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops)
110{
Aditya Angadie6508952019-07-21 22:13:45 +0530[diff] [blame]111 /*
Pranav Madhue0195fd2021-01-16 22:47:08 +0530[diff] [blame]112 * For RD-E1-Edge, only CPU power ON/OFF, PSCI platform callbacks are
113 * supported.
Aditya Angadie6508952019-07-21 22:13:45 +0530[diff] [blame]114 */
115 if (((sgi_plat_info.platform_id == RD_N1E1_EDGE_SID_VER_PART_NUM) &&
Pranav Madhue0195fd2021-01-16 22:47:08 +0530[diff] [blame]116 (sgi_plat_info.config_id == RD_E1_EDGE_CONFIG_ID))) {
Chandni Cherukuri2dfe1d02018-11-22 10:15:25 +0530[diff] [blame]117 ops->cpu_standby = NULL;
118 ops->system_off = NULL;
119 ops->system_reset = NULL;
120 ops->get_sys_suspend_power_state = NULL;
121 ops->pwr_domain_suspend = NULL;
122 ops->pwr_domain_suspend_finish = NULL;
123 }
124
Chandni Cherukurie4bf6a02018-11-14 13:43:59 +0530[diff] [blame]125 return css_scmi_override_pm_ops(ops);
126}