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Varun Wadekarb316e242015-05-19 16:48:04 +05301/*
2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
3 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Varun Wadekarb316e242015-05-19 16:48:04 +05305 */
6
Varun Wadekarb316e242015-05-19 16:48:04 +05307#include <assert.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00008
9#include <arch_helpers.h>
10#include <common/debug.h>
11#include <lib/mmio.h>
12
Varun Wadekarb316e242015-05-19 16:48:04 +053013#include <pmc.h>
14#include <tegra_def.h>
15
Anthony Zhouc33c1e32017-03-13 16:47:58 +080016#define RESET_ENABLE 0x10U
17
Varun Wadekarb316e242015-05-19 16:48:04 +053018/* Module IDs used during power ungate procedure */
Anthony Zhouc33c1e32017-03-13 16:47:58 +080019static const uint32_t pmc_cpu_powergate_id[4] = {
Varun Wadekar952a5552018-02-13 20:22:19 -080020 14, /* CPU 0 */
Varun Wadekarb316e242015-05-19 16:48:04 +053021 9, /* CPU 1 */
22 10, /* CPU 2 */
23 11 /* CPU 3 */
24};
25
26/*******************************************************************************
27 * Power ungate CPU to start the boot process. CPU reset vectors must be
28 * populated before calling this function.
29 ******************************************************************************/
Anthony Zhouc33c1e32017-03-13 16:47:58 +080030void tegra_pmc_cpu_on(int32_t cpu)
Varun Wadekarb316e242015-05-19 16:48:04 +053031{
32 uint32_t val;
33
34 /*
Varun Wadekarfccf8e02015-07-16 10:35:12 +053035 * Check if CPU is already power ungated
36 */
37 val = tegra_pmc_read_32(PMC_PWRGATE_STATUS);
Anthony Zhouc33c1e32017-03-13 16:47:58 +080038 if ((val & (1U << pmc_cpu_powergate_id[cpu])) == 0U) {
39 /*
40 * The PMC deasserts the START bit when it starts the power
41 * ungate process. Loop till no power toggle is in progress.
42 */
43 do {
44 val = tegra_pmc_read_32(PMC_PWRGATE_TOGGLE);
45 } while ((val & PMC_TOGGLE_START) != 0U);
Varun Wadekarb316e242015-05-19 16:48:04 +053046
Anthony Zhouc33c1e32017-03-13 16:47:58 +080047 /*
48 * Start the power ungate procedure
49 */
50 val = pmc_cpu_powergate_id[cpu] | PMC_TOGGLE_START;
51 tegra_pmc_write_32(PMC_PWRGATE_TOGGLE, val);
Varun Wadekarb316e242015-05-19 16:48:04 +053052
Anthony Zhouc33c1e32017-03-13 16:47:58 +080053 /*
54 * The PMC deasserts the START bit when it starts the power
55 * ungate process. Loop till powergate START bit is asserted.
56 */
57 do {
58 val = tegra_pmc_read_32(PMC_PWRGATE_TOGGLE);
59 } while ((val & (1U << 8)) != 0U);
Varun Wadekarb316e242015-05-19 16:48:04 +053060
Anthony Zhouc33c1e32017-03-13 16:47:58 +080061 /* loop till the CPU is power ungated */
62 do {
63 val = tegra_pmc_read_32(PMC_PWRGATE_STATUS);
64 } while ((val & (1U << pmc_cpu_powergate_id[cpu])) == 0U);
65 }
Varun Wadekarb316e242015-05-19 16:48:04 +053066}
67
68/*******************************************************************************
69 * Setup CPU vectors for resume from deep sleep
70 ******************************************************************************/
71void tegra_pmc_cpu_setup(uint64_t reset_addr)
72{
73 uint32_t val;
74
Anthony Zhouc33c1e32017-03-13 16:47:58 +080075 tegra_pmc_write_32(PMC_SECURE_SCRATCH34,
76 ((uint32_t)reset_addr & 0xFFFFFFFFU) | 1U);
77 val = (uint32_t)(reset_addr >> 32U);
78 tegra_pmc_write_32(PMC_SECURE_SCRATCH35, val & 0x7FFU);
Varun Wadekarb316e242015-05-19 16:48:04 +053079}
80
81/*******************************************************************************
82 * Lock CPU vectors to restrict further writes
83 ******************************************************************************/
84void tegra_pmc_lock_cpu_vectors(void)
85{
86 uint32_t val;
87
Varun Wadekar30d89772015-07-16 10:38:11 +053088 /* lock PMC_SECURE_SCRATCH22 */
89 val = tegra_pmc_read_32(PMC_SECURE_DISABLE2);
90 val |= PMC_SECURE_DISABLE2_WRITE22_ON;
91 tegra_pmc_write_32(PMC_SECURE_DISABLE2, val);
92
Varun Wadekarb316e242015-05-19 16:48:04 +053093 /* lock PMC_SECURE_SCRATCH34/35 */
94 val = tegra_pmc_read_32(PMC_SECURE_DISABLE3);
95 val |= (PMC_SECURE_DISABLE3_WRITE34_ON |
96 PMC_SECURE_DISABLE3_WRITE35_ON);
97 tegra_pmc_write_32(PMC_SECURE_DISABLE3, val);
98}
99
100/*******************************************************************************
Varun Wadekar952a5552018-02-13 20:22:19 -0800101 * Find out if this is the last standing CPU
102 ******************************************************************************/
103bool tegra_pmc_is_last_on_cpu(void)
104{
105 int i, cpu = read_mpidr() & MPIDR_CPU_MASK;
106 uint32_t val = tegra_pmc_read_32(PMC_PWRGATE_STATUS);;
107 bool status = true;
108
109 /* check if this is the last standing CPU */
110 for (i = 0; i < PLATFORM_MAX_CPUS_PER_CLUSTER; i++) {
111
112 /* skip the current CPU */
113 if (i == cpu)
114 continue;
115
116 /* are other CPUs already power gated? */
117 if ((val & ((uint32_t)1 << pmc_cpu_powergate_id[i])) != 0U) {
118 status = false;
119 }
120 }
121
122 return status;
123}
124
125/*******************************************************************************
kalyani chidambaramb3873aa2018-04-09 14:40:02 -0700126 * Handler to be called on exiting System suspend. Right now only DPD registers
127 * are cleared.
128 ******************************************************************************/
129void tegra_pmc_resume(void)
130{
131
132 /* Clear DPD sample */
133 mmio_write_32((TEGRA_PMC_BASE + PMC_IO_DPD_SAMPLE), 0x0);
134
135 /* Clear DPD Enable */
136 mmio_write_32((TEGRA_PMC_BASE + PMC_DPD_ENABLE_0), 0x0);
137}
138
139/*******************************************************************************
Varun Wadekarb316e242015-05-19 16:48:04 +0530140 * Restart the system
141 ******************************************************************************/
142__dead2 void tegra_pmc_system_reset(void)
143{
144 uint32_t reg;
145
146 reg = tegra_pmc_read_32(PMC_CONFIG);
Anthony Zhouc33c1e32017-03-13 16:47:58 +0800147 reg |= RESET_ENABLE; /* restart */
Varun Wadekarb316e242015-05-19 16:48:04 +0530148 tegra_pmc_write_32(PMC_CONFIG, reg);
149 wfi();
150
151 ERROR("Tegra System Reset: operation not handled.\n");
152 panic();
153}