| Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #include <arch_helpers.h> |
| 32 | #include <assert.h> |
| 33 | #include <debug.h> |
| 34 | #include <mmio.h> |
| 35 | #include <platform.h> |
| 36 | #include <platform_def.h> |
| 37 | #include <psci.h> |
| 38 | #include <pmc.h> |
| 39 | #include <flowctrl.h> |
| 40 | #include <tegra_def.h> |
| 41 | #include <tegra_private.h> |
| 42 | |
| 43 | /* Power down state IDs */ |
| 44 | #define PSTATE_ID_CORE_POWERDN 7 |
| 45 | #define PSTATE_ID_CLUSTER_IDLE 16 |
| 46 | #define PSTATE_ID_CLUSTER_POWERDN 17 |
| 47 | #define PSTATE_ID_SOC_POWERDN 27 |
| 48 | |
| 49 | static int cpu_powergate_mask[PLATFORM_MAX_CPUS_PER_CLUSTER]; |
| 50 | |
| 51 | int tegra_prepare_cpu_suspend(unsigned int id, unsigned int afflvl) |
| 52 | { |
| 53 | /* There's nothing to be done for affinity level 1 */ |
| 54 | if (afflvl == MPIDR_AFFLVL1) |
| 55 | return PSCI_E_SUCCESS; |
| 56 | |
| 57 | switch (id) { |
| 58 | /* Prepare for cpu idle */ |
| 59 | case PSTATE_ID_CORE_POWERDN: |
| 60 | tegra_fc_cpu_idle(read_mpidr()); |
| 61 | return PSCI_E_SUCCESS; |
| 62 | |
| 63 | /* Prepare for cluster idle */ |
| 64 | case PSTATE_ID_CLUSTER_IDLE: |
| 65 | tegra_fc_cluster_idle(read_mpidr()); |
| 66 | return PSCI_E_SUCCESS; |
| 67 | |
| 68 | /* Prepare for cluster powerdn */ |
| 69 | case PSTATE_ID_CLUSTER_POWERDN: |
| 70 | tegra_fc_cluster_powerdn(read_mpidr()); |
| 71 | return PSCI_E_SUCCESS; |
| 72 | |
| 73 | /* Prepare for system idle */ |
| 74 | case PSTATE_ID_SOC_POWERDN: |
| 75 | |
| 76 | /* Enter system suspend state */ |
| 77 | tegra_pm_system_suspend_entry(); |
| 78 | |
| 79 | /* suspend the entire soc */ |
| 80 | tegra_fc_soc_powerdn(read_mpidr()); |
| 81 | |
| 82 | return PSCI_E_SUCCESS; |
| 83 | |
| 84 | default: |
| 85 | ERROR("Unknown state id (%d)\n", id); |
| 86 | break; |
| 87 | } |
| 88 | |
| 89 | return PSCI_E_NOT_SUPPORTED; |
| 90 | } |
| 91 | |
| 92 | int tegra_prepare_cpu_on_finish(unsigned long mpidr) |
| 93 | { |
| 94 | /* |
| 95 | * Check if we are exiting from SOC_POWERDN. |
| 96 | */ |
| 97 | if (tegra_system_suspended()) { |
| 98 | |
| 99 | /* |
| 100 | * Restore Boot and Power Management Processor (BPMP) reset |
| 101 | * address and reset it. |
| 102 | */ |
| 103 | tegra_fc_reset_bpmp(); |
| 104 | |
| 105 | /* |
| 106 | * System resume complete. |
| 107 | */ |
| 108 | tegra_pm_system_suspend_exit(); |
| 109 | } |
| 110 | |
| 111 | /* |
| 112 | * T210 has a dedicated ARMv7 boot and power mgmt processor, BPMP. It's |
| 113 | * used for power management and boot purposes. Inform the BPMP that |
| 114 | * we have completed the cluster power up. |
| 115 | */ |
| 116 | if (psci_get_max_phys_off_afflvl() == MPIDR_AFFLVL1) |
| 117 | tegra_fc_lock_active_cluster(); |
| 118 | |
| 119 | return PSCI_E_SUCCESS; |
| 120 | } |
| 121 | |
| 122 | int tegra_prepare_cpu_on(unsigned long mpidr) |
| 123 | { |
| 124 | int cpu = mpidr & MPIDR_CPU_MASK; |
| 125 | |
| 126 | /* Turn on CPU using flow controller or PMC */ |
| 127 | if (cpu_powergate_mask[cpu] == 0) { |
| 128 | tegra_pmc_cpu_on(cpu); |
| 129 | cpu_powergate_mask[cpu] = 1; |
| 130 | } else { |
| 131 | tegra_fc_cpu_on(cpu); |
| 132 | } |
| 133 | |
| 134 | return PSCI_E_SUCCESS; |
| 135 | } |
| 136 | |
| 137 | int tegra_prepare_cpu_off(unsigned long mpidr) |
| 138 | { |
| 139 | tegra_fc_cpu_off(mpidr & MPIDR_CPU_MASK); |
| 140 | return PSCI_E_SUCCESS; |
| 141 | } |