blob: 5a49b4f5ed34e44a0dca0dd05974f36a379457ea [file] [log] [blame]
Achin Gupta92712a52015-09-03 14:18:02 +01001/*
Heyi Guo3a579ae2020-05-19 11:50:40 +08002 * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
Achin Gupta92712a52015-09-03 14:18:02 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta92712a52015-09-03 14:18:02 +01005 */
6
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00007#include <assert.h>
8
Achin Gupta92712a52015-09-03 14:18:02 +01009#include <arch.h>
10#include <arch_helpers.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000011#include <common/debug.h>
12#include <common/interrupt_props.h>
13#include <drivers/arm/gicv3.h>
14#include <lib/spinlock.h>
15
Achin Gupta92712a52015-09-03 14:18:02 +010016#include "gicv3_private.h"
17
Jeenu Viswambharand7a901e2016-12-06 16:15:22 +000018const gicv3_driver_data_t *gicv3_driver_data;
Achin Gupta92712a52015-09-03 14:18:02 +010019
Jeenu Viswambharan76647d52016-12-09 11:03:15 +000020/*
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +010021 * Spinlock to guard registers needing read-modify-write. APIs protected by this
22 * spinlock are used either at boot time (when only a single CPU is active), or
23 * when the system is fully coherent.
24 */
Roberto Vargas2ca18d92018-02-12 12:36:17 +000025static spinlock_t gic_lock;
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +010026
27/*
Jeenu Viswambharan76647d52016-12-09 11:03:15 +000028 * Redistributor power operations are weakly bound so that they can be
29 * overridden
30 */
31#pragma weak gicv3_rdistif_off
32#pragma weak gicv3_rdistif_on
33
Alexei Fedorova6e6ae02020-04-06 16:27:54 +010034/* Check interrupt ID for SGI/(E)PPI and (E)SPIs */
35static bool is_sgi_ppi(unsigned int id);
36
37/*
38 * Helper macros to save and restore GICR and GICD registers
39 * corresponding to their numbers to and from the context
40 */
41#define RESTORE_GICR_REG(base, ctx, name, i) \
42 gicr_write_##name((base), (i), (ctx)->gicr_##name[(i)])
43
44#define SAVE_GICR_REG(base, ctx, name, i) \
45 (ctx)->gicr_##name[(i)] = gicr_read_##name((base), (i))
Soby Mathew327548c2017-07-13 15:19:51 +010046
47/* Helper macros to save and restore GICD registers to and from the context */
48#define RESTORE_GICD_REGS(base, ctx, intr_num, reg, REG) \
49 do { \
Alexei Fedorova6e6ae02020-04-06 16:27:54 +010050 for (unsigned int int_id = MIN_SPI_ID; int_id < (intr_num);\
51 int_id += (1U << REG##R_SHIFT)) { \
52 gicd_write_##reg((base), int_id, \
53 (ctx)->gicd_##reg[(int_id - MIN_SPI_ID) >> \
54 REG##R_SHIFT]); \
Soby Mathew327548c2017-07-13 15:19:51 +010055 } \
Antonio Nino Diazca994e72018-08-21 10:02:33 +010056 } while (false)
Soby Mathew327548c2017-07-13 15:19:51 +010057
58#define SAVE_GICD_REGS(base, ctx, intr_num, reg, REG) \
59 do { \
Alexei Fedorova6e6ae02020-04-06 16:27:54 +010060 for (unsigned int int_id = MIN_SPI_ID; int_id < (intr_num);\
61 int_id += (1U << REG##R_SHIFT)) { \
62 (ctx)->gicd_##reg[(int_id - MIN_SPI_ID) >> \
63 REG##R_SHIFT] = gicd_read_##reg((base), int_id); \
64 } \
65 } while (false)
66
67#if GIC_EXT_INTID
68#define RESTORE_GICD_EREGS(base, ctx, intr_num, reg, REG) \
69 do { \
70 for (unsigned int int_id = MIN_ESPI_ID; int_id < (intr_num);\
71 int_id += (1U << REG##R_SHIFT)) { \
72 gicd_write_##reg((base), int_id, \
Heyi Guoefa21072021-01-14 22:16:18 +080073 (ctx)->gicd_##reg[(int_id - (MIN_ESPI_ID - \
74 round_up(TOTAL_SPI_INTR_NUM, 1U << REG##R_SHIFT)))\
Alexei Fedorova6e6ae02020-04-06 16:27:54 +010075 >> REG##R_SHIFT]); \
Soby Mathew327548c2017-07-13 15:19:51 +010076 } \
Antonio Nino Diazca994e72018-08-21 10:02:33 +010077 } while (false)
Soby Mathew327548c2017-07-13 15:19:51 +010078
Alexei Fedorova6e6ae02020-04-06 16:27:54 +010079#define SAVE_GICD_EREGS(base, ctx, intr_num, reg, REG) \
80 do { \
81 for (unsigned int int_id = MIN_ESPI_ID; int_id < (intr_num);\
82 int_id += (1U << REG##R_SHIFT)) { \
Heyi Guoefa21072021-01-14 22:16:18 +080083 (ctx)->gicd_##reg[(int_id - (MIN_ESPI_ID - \
84 round_up(TOTAL_SPI_INTR_NUM, 1U << REG##R_SHIFT)))\
Alexei Fedorova6e6ae02020-04-06 16:27:54 +010085 >> REG##R_SHIFT] = gicd_read_##reg((base), int_id);\
86 } \
87 } while (false)
88#else
89#define SAVE_GICD_EREGS(base, ctx, intr_num, reg, REG)
90#define RESTORE_GICD_EREGS(base, ctx, intr_num, reg, REG)
91#endif /* GIC_EXT_INTID */
Soby Mathew327548c2017-07-13 15:19:51 +010092
Achin Gupta92712a52015-09-03 14:18:02 +010093/*******************************************************************************
94 * This function initialises the ARM GICv3 driver in EL3 with provided platform
95 * inputs.
96 ******************************************************************************/
Daniel Boulby844b4872018-09-18 13:36:39 +010097void __init gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data)
Achin Gupta92712a52015-09-03 14:18:02 +010098{
99 unsigned int gic_version;
Madhukar Pappireddy5fd1f9d2019-05-15 18:25:41 -0500100 unsigned int gicv2_compat;
Achin Gupta92712a52015-09-03 14:18:02 +0100101
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100102 assert(plat_driver_data != NULL);
103 assert(plat_driver_data->gicd_base != 0U);
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100104 assert(plat_driver_data->rdistif_num != 0U);
105 assert(plat_driver_data->rdistif_base_addrs != NULL);
Achin Gupta92712a52015-09-03 14:18:02 +0100106
107 assert(IS_IN_EL3());
108
Madhukar Pappireddy5fd1f9d2019-05-15 18:25:41 -0500109 assert((plat_driver_data->interrupt_props_num != 0U) ?
110 (plat_driver_data->interrupt_props != NULL) : 1);
Achin Gupta92712a52015-09-03 14:18:02 +0100111
112 /* Check for system register support */
Madhukar Pappireddy5fd1f9d2019-05-15 18:25:41 -0500113#ifndef __aarch64__
114 assert((read_id_pfr1() &
115 (ID_PFR1_GIC_MASK << ID_PFR1_GIC_SHIFT)) != 0U);
116#else
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100117 assert((read_id_aa64pfr0_el1() &
118 (ID_AA64PFR0_GIC_MASK << ID_AA64PFR0_GIC_SHIFT)) != 0U);
Madhukar Pappireddy5fd1f9d2019-05-15 18:25:41 -0500119#endif /* !__aarch64__ */
Achin Gupta92712a52015-09-03 14:18:02 +0100120
Achin Gupta92712a52015-09-03 14:18:02 +0100121 gic_version = gicd_read_pidr2(plat_driver_data->gicd_base);
Madhukar Pappireddy5fd1f9d2019-05-15 18:25:41 -0500122 gic_version >>= PIDR2_ARCH_REV_SHIFT;
Achin Gupta92712a52015-09-03 14:18:02 +0100123 gic_version &= PIDR2_ARCH_REV_MASK;
Achin Gupta92712a52015-09-03 14:18:02 +0100124
Alexei Fedorov19705932020-04-06 19:00:35 +0100125 /* Check GIC version */
126#if GIC_ENABLE_V4_EXTN
127 assert(gic_version == ARCH_REV_GICV4);
128
129 /* GICv4 supports Direct Virtual LPI injection */
130 assert((gicd_read_typer(plat_driver_data->gicd_base)
131 & TYPER_DVIS) != 0);
132#else
133 assert(gic_version == ARCH_REV_GICV3);
134#endif
Achin Gupta92712a52015-09-03 14:18:02 +0100135 /*
Madhukar Pappireddy5fd1f9d2019-05-15 18:25:41 -0500136 * Find out whether the GIC supports the GICv2 compatibility mode.
137 * The ARE_S bit resets to 0 if supported
Achin Gupta92712a52015-09-03 14:18:02 +0100138 */
139 gicv2_compat = gicd_read_ctlr(plat_driver_data->gicd_base);
140 gicv2_compat >>= CTLR_ARE_S_SHIFT;
Madhukar Pappireddy5fd1f9d2019-05-15 18:25:41 -0500141 gicv2_compat = gicv2_compat & CTLR_ARE_S_MASK;
Achin Gupta92712a52015-09-03 14:18:02 +0100142
Madhukar Pappireddy5fd1f9d2019-05-15 18:25:41 -0500143 if (plat_driver_data->gicr_base != 0U) {
144 /*
145 * Find the base address of each implemented Redistributor interface.
146 * The number of interfaces should be equal to the number of CPUs in the
147 * system. The memory for saving these addresses has to be allocated by
148 * the platform port
149 */
150 gicv3_rdistif_base_addrs_probe(plat_driver_data->rdistif_base_addrs,
151 plat_driver_data->rdistif_num,
152 plat_driver_data->gicr_base,
153 plat_driver_data->mpidr_to_core_pos);
154#if !HW_ASSISTED_COHERENCY
155 /*
156 * Flush the rdistif_base_addrs[] contents linked to the GICv3 driver.
157 */
158 flush_dcache_range((uintptr_t)(plat_driver_data->rdistif_base_addrs),
159 plat_driver_data->rdistif_num *
160 sizeof(*(plat_driver_data->rdistif_base_addrs)));
161#endif
162 }
Jeenu Viswambharand7a901e2016-12-06 16:15:22 +0000163 gicv3_driver_data = plat_driver_data;
Achin Gupta92712a52015-09-03 14:18:02 +0100164
Soby Mathew72645132017-02-14 10:11:52 +0000165 /*
166 * The GIC driver data is initialized by the primary CPU with caches
167 * enabled. When the secondary CPU boots up, it initializes the
168 * GICC/GICR interface with the caches disabled. Hence flush the
Jeenu Viswambharand7a901e2016-12-06 16:15:22 +0000169 * driver data to ensure coherency. This is not required if the
Madhukar Pappireddy5fd1f9d2019-05-15 18:25:41 -0500170 * platform has HW_ASSISTED_COHERENCY enabled.
Soby Mathew72645132017-02-14 10:11:52 +0000171 */
Madhukar Pappireddy5fd1f9d2019-05-15 18:25:41 -0500172#if !HW_ASSISTED_COHERENCY
173 flush_dcache_range((uintptr_t)&gicv3_driver_data,
174 sizeof(gicv3_driver_data));
175 flush_dcache_range((uintptr_t)gicv3_driver_data,
176 sizeof(*gicv3_driver_data));
Soby Mathew72645132017-02-14 10:11:52 +0000177#endif
Alexei Fedorov19705932020-04-06 19:00:35 +0100178 INFO("GICv%u with%s legacy support detected.\n", gic_version,
179 (gicv2_compat == 0U) ? "" : "out");
180 INFO("ARM GICv%u driver initialized in EL3\n", gic_version);
Achin Gupta92712a52015-09-03 14:18:02 +0100181}
182
183/*******************************************************************************
184 * This function initialises the GIC distributor interface based upon the data
185 * provided by the platform while initialising the driver.
186 ******************************************************************************/
Daniel Boulby844b4872018-09-18 13:36:39 +0100187void __init gicv3_distif_init(void)
Achin Gupta92712a52015-09-03 14:18:02 +0100188{
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100189 unsigned int bitmap;
Yatharth Kochar3f00a892016-09-06 11:48:05 +0100190
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100191 assert(gicv3_driver_data != NULL);
192 assert(gicv3_driver_data->gicd_base != 0U);
Achin Gupta92712a52015-09-03 14:18:02 +0100193
194 assert(IS_IN_EL3());
195
196 /*
197 * Clear the "enable" bits for G0/G1S/G1NS interrupts before configuring
198 * the ARE_S bit. The Distributor might generate a system error
199 * otherwise.
200 */
Jeenu Viswambharand7a901e2016-12-06 16:15:22 +0000201 gicd_clr_ctlr(gicv3_driver_data->gicd_base,
Achin Gupta92712a52015-09-03 14:18:02 +0100202 CTLR_ENABLE_G0_BIT |
203 CTLR_ENABLE_G1S_BIT |
204 CTLR_ENABLE_G1NS_BIT,
205 RWP_TRUE);
206
207 /* Set the ARE_S and ARE_NS bit now that interrupts have been disabled */
Jeenu Viswambharand7a901e2016-12-06 16:15:22 +0000208 gicd_set_ctlr(gicv3_driver_data->gicd_base,
Achin Gupta92712a52015-09-03 14:18:02 +0100209 CTLR_ARE_S_BIT | CTLR_ARE_NS_BIT, RWP_TRUE);
210
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100211 /* Set the default attribute of all (E)SPIs */
Daniel Boulby4e83abb2018-05-01 15:15:34 +0100212 gicv3_spis_config_defaults(gicv3_driver_data->gicd_base);
Achin Gupta92712a52015-09-03 14:18:02 +0100213
Antonio Nino Diaz29b9f5b2018-09-24 17:23:24 +0100214 bitmap = gicv3_secure_spis_config_props(
215 gicv3_driver_data->gicd_base,
216 gicv3_driver_data->interrupt_props,
217 gicv3_driver_data->interrupt_props_num);
Achin Gupta92712a52015-09-03 14:18:02 +0100218
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100219 /* Enable the secure (E)SPIs now that they have been configured */
Jeenu Viswambharand7a901e2016-12-06 16:15:22 +0000220 gicd_set_ctlr(gicv3_driver_data->gicd_base, bitmap, RWP_TRUE);
Achin Gupta92712a52015-09-03 14:18:02 +0100221}
222
223/*******************************************************************************
224 * This function initialises the GIC Redistributor interface of the calling CPU
225 * (identified by the 'proc_num' parameter) based upon the data provided by the
226 * platform while initialising the driver.
227 ******************************************************************************/
228void gicv3_rdistif_init(unsigned int proc_num)
229{
230 uintptr_t gicr_base;
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100231 unsigned int bitmap;
Jeenu Viswambharan88d8f452017-11-07 08:38:23 +0000232 uint32_t ctlr;
Achin Gupta92712a52015-09-03 14:18:02 +0100233
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100234 assert(gicv3_driver_data != NULL);
Jeenu Viswambharand7a901e2016-12-06 16:15:22 +0000235 assert(proc_num < gicv3_driver_data->rdistif_num);
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100236 assert(gicv3_driver_data->rdistif_base_addrs != NULL);
237 assert(gicv3_driver_data->gicd_base != 0U);
Jeenu Viswambharan88d8f452017-11-07 08:38:23 +0000238
239 ctlr = gicd_read_ctlr(gicv3_driver_data->gicd_base);
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100240 assert((ctlr & CTLR_ARE_S_BIT) != 0U);
Achin Gupta92712a52015-09-03 14:18:02 +0100241
242 assert(IS_IN_EL3());
243
Jeenu Viswambharan76647d52016-12-09 11:03:15 +0000244 /* Power on redistributor */
245 gicv3_rdistif_on(proc_num);
246
Jeenu Viswambharand7a901e2016-12-06 16:15:22 +0000247 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
Madhukar Pappireddy5fd1f9d2019-05-15 18:25:41 -0500248 assert(gicr_base != 0U);
Achin Gupta92712a52015-09-03 14:18:02 +0100249
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100250 /* Set the default attribute of all SGIs and (E)PPIs */
Daniel Boulby4e83abb2018-05-01 15:15:34 +0100251 gicv3_ppi_sgi_config_defaults(gicr_base);
Achin Gupta92712a52015-09-03 14:18:02 +0100252
Antonio Nino Diaz29b9f5b2018-09-24 17:23:24 +0100253 bitmap = gicv3_secure_ppi_sgi_config_props(gicr_base,
254 gicv3_driver_data->interrupt_props,
255 gicv3_driver_data->interrupt_props_num);
Jeenu Viswambharan88d8f452017-11-07 08:38:23 +0000256
257 /* Enable interrupt groups as required, if not already */
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100258 if ((ctlr & bitmap) != bitmap) {
Jeenu Viswambharan88d8f452017-11-07 08:38:23 +0000259 gicd_set_ctlr(gicv3_driver_data->gicd_base, bitmap, RWP_TRUE);
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100260 }
Achin Gupta92712a52015-09-03 14:18:02 +0100261}
262
263/*******************************************************************************
Jeenu Viswambharan76647d52016-12-09 11:03:15 +0000264 * Functions to perform power operations on GIC Redistributor
265 ******************************************************************************/
266void gicv3_rdistif_off(unsigned int proc_num)
267{
Jeenu Viswambharan76647d52016-12-09 11:03:15 +0000268}
269
270void gicv3_rdistif_on(unsigned int proc_num)
271{
Jeenu Viswambharan76647d52016-12-09 11:03:15 +0000272}
273
274/*******************************************************************************
Achin Gupta92712a52015-09-03 14:18:02 +0100275 * This function enables the GIC CPU interface of the calling CPU using only
276 * system register accesses.
277 ******************************************************************************/
278void gicv3_cpuif_enable(unsigned int proc_num)
279{
280 uintptr_t gicr_base;
Louis Mayencourt1c819c32020-01-24 13:30:28 +0000281 u_register_t scr_el3;
Achin Gupta92712a52015-09-03 14:18:02 +0100282 unsigned int icc_sre_el3;
283
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100284 assert(gicv3_driver_data != NULL);
Jeenu Viswambharand7a901e2016-12-06 16:15:22 +0000285 assert(proc_num < gicv3_driver_data->rdistif_num);
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100286 assert(gicv3_driver_data->rdistif_base_addrs != NULL);
Achin Gupta92712a52015-09-03 14:18:02 +0100287 assert(IS_IN_EL3());
288
289 /* Mark the connected core as awake */
Jeenu Viswambharand7a901e2016-12-06 16:15:22 +0000290 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
Achin Gupta92712a52015-09-03 14:18:02 +0100291 gicv3_rdistif_mark_core_awake(gicr_base);
292
293 /* Disable the legacy interrupt bypass */
294 icc_sre_el3 = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT;
295
296 /*
297 * Enable system register access for EL3 and allow lower exception
298 * levels to configure the same for themselves. If the legacy mode is
299 * not supported, the SRE bit is RAO/WI
300 */
301 icc_sre_el3 |= (ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT);
302 write_icc_sre_el3(read_icc_sre_el3() | icc_sre_el3);
303
Louis Mayencourt1c819c32020-01-24 13:30:28 +0000304 scr_el3 = read_scr_el3();
Achin Gupta92712a52015-09-03 14:18:02 +0100305
306 /*
307 * Switch to NS state to write Non secure ICC_SRE_EL1 and
308 * ICC_SRE_EL2 registers.
309 */
310 write_scr_el3(scr_el3 | SCR_NS_BIT);
311 isb();
312
313 write_icc_sre_el2(read_icc_sre_el2() | icc_sre_el3);
314 write_icc_sre_el1(ICC_SRE_SRE_BIT);
315 isb();
316
317 /* Switch to secure state. */
318 write_scr_el3(scr_el3 & (~SCR_NS_BIT));
319 isb();
320
James kung05403eb2019-05-31 15:40:05 +0800321 /* Write the secure ICC_SRE_EL1 register */
322 write_icc_sre_el1(ICC_SRE_SRE_BIT);
323 isb();
324
Achin Gupta92712a52015-09-03 14:18:02 +0100325 /* Program the idle priority in the PMR */
326 write_icc_pmr_el1(GIC_PRI_MASK);
327
328 /* Enable Group0 interrupts */
329 write_icc_igrpen0_el1(IGRPEN1_EL1_ENABLE_G0_BIT);
330
331 /* Enable Group1 Secure interrupts */
332 write_icc_igrpen1_el3(read_icc_igrpen1_el3() |
333 IGRPEN1_EL3_ENABLE_G1S_BIT);
Achin Gupta92712a52015-09-03 14:18:02 +0100334 isb();
335}
336
337/*******************************************************************************
338 * This function disables the GIC CPU interface of the calling CPU using
339 * only system register accesses.
340 ******************************************************************************/
341void gicv3_cpuif_disable(unsigned int proc_num)
342{
343 uintptr_t gicr_base;
344
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100345 assert(gicv3_driver_data != NULL);
Jeenu Viswambharand7a901e2016-12-06 16:15:22 +0000346 assert(proc_num < gicv3_driver_data->rdistif_num);
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100347 assert(gicv3_driver_data->rdistif_base_addrs != NULL);
Achin Gupta92712a52015-09-03 14:18:02 +0100348
349 assert(IS_IN_EL3());
350
351 /* Disable legacy interrupt bypass */
352 write_icc_sre_el3(read_icc_sre_el3() |
353 (ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT));
354
355 /* Disable Group0 interrupts */
356 write_icc_igrpen0_el1(read_icc_igrpen0_el1() &
357 ~IGRPEN1_EL1_ENABLE_G0_BIT);
358
Sudeep Holla869e3db2016-08-04 16:14:50 +0100359 /* Disable Group1 Secure and Non-Secure interrupts */
Achin Gupta92712a52015-09-03 14:18:02 +0100360 write_icc_igrpen1_el3(read_icc_igrpen1_el3() &
Sudeep Holla869e3db2016-08-04 16:14:50 +0100361 ~(IGRPEN1_EL3_ENABLE_G1NS_BIT |
362 IGRPEN1_EL3_ENABLE_G1S_BIT));
Achin Gupta92712a52015-09-03 14:18:02 +0100363
364 /* Synchronise accesses to group enable registers */
365 isb();
366
367 /* Mark the connected core as asleep */
Jeenu Viswambharand7a901e2016-12-06 16:15:22 +0000368 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
Madhukar Pappireddy5fd1f9d2019-05-15 18:25:41 -0500369 assert(gicr_base != 0U);
Achin Gupta92712a52015-09-03 14:18:02 +0100370 gicv3_rdistif_mark_core_asleep(gicr_base);
371}
372
373/*******************************************************************************
374 * This function returns the id of the highest priority pending interrupt at
375 * the GIC cpu interface.
376 ******************************************************************************/
377unsigned int gicv3_get_pending_interrupt_id(void)
378{
379 unsigned int id;
380
381 assert(IS_IN_EL3());
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100382 id = (uint32_t)read_icc_hppir0_el1() & HPPIR0_EL1_INTID_MASK;
Achin Gupta92712a52015-09-03 14:18:02 +0100383
384 /*
385 * If the ID is special identifier corresponding to G1S or G1NS
386 * interrupt, then read the highest pending group 1 interrupt.
387 */
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100388 if ((id == PENDING_G1S_INTID) || (id == PENDING_G1NS_INTID)) {
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100389 return (uint32_t)read_icc_hppir1_el1() & HPPIR1_EL1_INTID_MASK;
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100390 }
Achin Gupta92712a52015-09-03 14:18:02 +0100391
392 return id;
393}
394
395/*******************************************************************************
396 * This function returns the type of the highest priority pending interrupt at
397 * the GIC cpu interface. The return values can be one of the following :
398 * PENDING_G1S_INTID : The interrupt type is secure Group 1.
399 * PENDING_G1NS_INTID : The interrupt type is non secure Group 1.
400 * 0 - 1019 : The interrupt type is secure Group 0.
401 * GIC_SPURIOUS_INTERRUPT : there is no pending interrupt with
402 * sufficient priority to be signaled
403 ******************************************************************************/
404unsigned int gicv3_get_pending_interrupt_type(void)
405{
406 assert(IS_IN_EL3());
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100407 return (uint32_t)read_icc_hppir0_el1() & HPPIR0_EL1_INTID_MASK;
Achin Gupta92712a52015-09-03 14:18:02 +0100408}
409
410/*******************************************************************************
411 * This function returns the type of the interrupt id depending upon the group
412 * this interrupt has been configured under by the interrupt controller i.e.
413 * group0 or group1 Secure / Non Secure. The return value can be one of the
414 * following :
Soby Mathew5c5c36b2015-12-03 14:12:54 +0000415 * INTR_GROUP0 : The interrupt type is a Secure Group 0 interrupt
416 * INTR_GROUP1S : The interrupt type is a Secure Group 1 secure interrupt
417 * INTR_GROUP1NS: The interrupt type is a Secure Group 1 non secure
Achin Gupta92712a52015-09-03 14:18:02 +0100418 * interrupt.
419 ******************************************************************************/
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100420unsigned int gicv3_get_interrupt_type(unsigned int id, unsigned int proc_num)
Achin Gupta92712a52015-09-03 14:18:02 +0100421{
422 unsigned int igroup, grpmodr;
423 uintptr_t gicr_base;
424
425 assert(IS_IN_EL3());
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100426 assert(gicv3_driver_data != NULL);
Achin Gupta92712a52015-09-03 14:18:02 +0100427
428 /* Ensure the parameters are valid */
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100429 assert((id < PENDING_G1S_INTID) || (id >= MIN_LPI_ID));
Jeenu Viswambharand7a901e2016-12-06 16:15:22 +0000430 assert(proc_num < gicv3_driver_data->rdistif_num);
Achin Gupta92712a52015-09-03 14:18:02 +0100431
432 /* All LPI interrupts are Group 1 non secure */
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100433 if (id >= MIN_LPI_ID) {
Soby Mathew5c5c36b2015-12-03 14:12:54 +0000434 return INTR_GROUP1NS;
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100435 }
Achin Gupta92712a52015-09-03 14:18:02 +0100436
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100437 /* Check interrupt ID */
438 if (is_sgi_ppi(id)) {
439 /* SGIs: 0-15, PPIs: 16-31, EPPIs: 1056-1119 */
Andrew F. Davis25a17a22018-08-30 14:30:54 -0500440 assert(gicv3_driver_data->rdistif_base_addrs != NULL);
Jeenu Viswambharand7a901e2016-12-06 16:15:22 +0000441 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100442 igroup = gicr_get_igroupr(gicr_base, id);
443 grpmodr = gicr_get_igrpmodr(gicr_base, id);
Achin Gupta92712a52015-09-03 14:18:02 +0100444 } else {
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100445 /* SPIs: 32-1019, ESPIs: 4096-5119 */
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100446 assert(gicv3_driver_data->gicd_base != 0U);
Jeenu Viswambharand7a901e2016-12-06 16:15:22 +0000447 igroup = gicd_get_igroupr(gicv3_driver_data->gicd_base, id);
448 grpmodr = gicd_get_igrpmodr(gicv3_driver_data->gicd_base, id);
Achin Gupta92712a52015-09-03 14:18:02 +0100449 }
450
451 /*
452 * If the IGROUP bit is set, then it is a Group 1 Non secure
453 * interrupt
454 */
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100455 if (igroup != 0U) {
Soby Mathew5c5c36b2015-12-03 14:12:54 +0000456 return INTR_GROUP1NS;
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100457 }
Achin Gupta92712a52015-09-03 14:18:02 +0100458
459 /* If the GRPMOD bit is set, then it is a Group 1 Secure interrupt */
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100460 if (grpmodr != 0U) {
Soby Mathew5c5c36b2015-12-03 14:12:54 +0000461 return INTR_GROUP1S;
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100462 }
Achin Gupta92712a52015-09-03 14:18:02 +0100463
464 /* Else it is a Group 0 Secure interrupt */
Soby Mathew5c5c36b2015-12-03 14:12:54 +0000465 return INTR_GROUP0;
Achin Gupta92712a52015-09-03 14:18:02 +0100466}
Soby Mathew327548c2017-07-13 15:19:51 +0100467
468/*****************************************************************************
Soby Mathewf6f1a322017-07-18 16:12:45 +0100469 * Function to save and disable the GIC ITS register context. The power
470 * management of GIC ITS is implementation-defined and this function doesn't
471 * save any memory structures required to support ITS. As the sequence to save
472 * this state is implementation defined, it should be executed in platform
473 * specific code. Calling this function alone and then powering down the GIC and
474 * ITS without implementing the aforementioned platform specific code will
475 * corrupt the ITS state.
476 *
477 * This function must be invoked after the GIC CPU interface is disabled.
478 *****************************************************************************/
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100479void gicv3_its_save_disable(uintptr_t gits_base,
480 gicv3_its_ctx_t * const its_ctx)
Soby Mathewf6f1a322017-07-18 16:12:45 +0100481{
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100482 unsigned int i;
Soby Mathewf6f1a322017-07-18 16:12:45 +0100483
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100484 assert(gicv3_driver_data != NULL);
Soby Mathewf6f1a322017-07-18 16:12:45 +0100485 assert(IS_IN_EL3());
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100486 assert(its_ctx != NULL);
487 assert(gits_base != 0U);
Soby Mathewf6f1a322017-07-18 16:12:45 +0100488
489 its_ctx->gits_ctlr = gits_read_ctlr(gits_base);
490
491 /* Disable the ITS */
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100492 gits_write_ctlr(gits_base, its_ctx->gits_ctlr & ~GITS_CTLR_ENABLED_BIT);
Soby Mathewf6f1a322017-07-18 16:12:45 +0100493
494 /* Wait for quiescent state */
495 gits_wait_for_quiescent_bit(gits_base);
496
497 its_ctx->gits_cbaser = gits_read_cbaser(gits_base);
498 its_ctx->gits_cwriter = gits_read_cwriter(gits_base);
499
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100500 for (i = 0U; i < ARRAY_SIZE(its_ctx->gits_baser); i++) {
Soby Mathewf6f1a322017-07-18 16:12:45 +0100501 its_ctx->gits_baser[i] = gits_read_baser(gits_base, i);
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100502 }
Soby Mathewf6f1a322017-07-18 16:12:45 +0100503}
504
505/*****************************************************************************
506 * Function to restore the GIC ITS register context. The power
507 * management of GIC ITS is implementation defined and this function doesn't
508 * restore any memory structures required to support ITS. The assumption is
509 * that these structures are in memory and are retained during system suspend.
510 *
511 * This must be invoked before the GIC CPU interface is enabled.
512 *****************************************************************************/
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100513void gicv3_its_restore(uintptr_t gits_base,
514 const gicv3_its_ctx_t * const its_ctx)
Soby Mathewf6f1a322017-07-18 16:12:45 +0100515{
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100516 unsigned int i;
Soby Mathewf6f1a322017-07-18 16:12:45 +0100517
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100518 assert(gicv3_driver_data != NULL);
Soby Mathewf6f1a322017-07-18 16:12:45 +0100519 assert(IS_IN_EL3());
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100520 assert(its_ctx != NULL);
521 assert(gits_base != 0U);
Soby Mathewf6f1a322017-07-18 16:12:45 +0100522
523 /* Assert that the GITS is disabled and quiescent */
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100524 assert((gits_read_ctlr(gits_base) & GITS_CTLR_ENABLED_BIT) == 0U);
525 assert((gits_read_ctlr(gits_base) & GITS_CTLR_QUIESCENT_BIT) != 0U);
Soby Mathewf6f1a322017-07-18 16:12:45 +0100526
527 gits_write_cbaser(gits_base, its_ctx->gits_cbaser);
528 gits_write_cwriter(gits_base, its_ctx->gits_cwriter);
529
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100530 for (i = 0U; i < ARRAY_SIZE(its_ctx->gits_baser); i++) {
Soby Mathewf6f1a322017-07-18 16:12:45 +0100531 gits_write_baser(gits_base, i, its_ctx->gits_baser[i]);
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100532 }
Soby Mathewf6f1a322017-07-18 16:12:45 +0100533
534 /* Restore the ITS CTLR but leave the ITS disabled */
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100535 gits_write_ctlr(gits_base, its_ctx->gits_ctlr & ~GITS_CTLR_ENABLED_BIT);
Soby Mathewf6f1a322017-07-18 16:12:45 +0100536}
537
538/*****************************************************************************
Soby Mathew327548c2017-07-13 15:19:51 +0100539 * Function to save the GIC Redistributor register context. This function
540 * must be invoked after CPU interface disable and prior to Distributor save.
541 *****************************************************************************/
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100542void gicv3_rdistif_save(unsigned int proc_num,
543 gicv3_redist_ctx_t * const rdist_ctx)
Soby Mathew327548c2017-07-13 15:19:51 +0100544{
545 uintptr_t gicr_base;
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100546 unsigned int i, ppi_regs_num, regs_num;
Soby Mathew327548c2017-07-13 15:19:51 +0100547
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100548 assert(gicv3_driver_data != NULL);
Soby Mathew327548c2017-07-13 15:19:51 +0100549 assert(proc_num < gicv3_driver_data->rdistif_num);
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100550 assert(gicv3_driver_data->rdistif_base_addrs != NULL);
Soby Mathew327548c2017-07-13 15:19:51 +0100551 assert(IS_IN_EL3());
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100552 assert(rdist_ctx != NULL);
Soby Mathew327548c2017-07-13 15:19:51 +0100553
554 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
555
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100556#if GIC_EXT_INTID
557 /* Calculate number of PPI registers */
558 ppi_regs_num = (unsigned int)((gicr_read_typer(gicr_base) >>
559 TYPER_PPI_NUM_SHIFT) & TYPER_PPI_NUM_MASK) + 1;
560 /* All other values except PPInum [0-2] are reserved */
561 if (ppi_regs_num > 3U) {
562 ppi_regs_num = 1U;
563 }
564#else
565 ppi_regs_num = 1U;
566#endif
Soby Mathew327548c2017-07-13 15:19:51 +0100567 /*
568 * Wait for any write to GICR_CTLR to complete before trying to save any
569 * state.
570 */
571 gicr_wait_for_pending_write(gicr_base);
572
573 rdist_ctx->gicr_ctlr = gicr_read_ctlr(gicr_base);
574
575 rdist_ctx->gicr_propbaser = gicr_read_propbaser(gicr_base);
576 rdist_ctx->gicr_pendbaser = gicr_read_pendbaser(gicr_base);
577
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100578 /* 32 interrupt IDs per register */
579 for (i = 0U; i < ppi_regs_num; ++i) {
580 SAVE_GICR_REG(gicr_base, rdist_ctx, igroupr, i);
581 SAVE_GICR_REG(gicr_base, rdist_ctx, isenabler, i);
582 SAVE_GICR_REG(gicr_base, rdist_ctx, ispendr, i);
583 SAVE_GICR_REG(gicr_base, rdist_ctx, isactiver, i);
584 SAVE_GICR_REG(gicr_base, rdist_ctx, igrpmodr, i);
Soby Mathew327548c2017-07-13 15:19:51 +0100585 }
586
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100587 /* 16 interrupt IDs per GICR_ICFGR register */
588 regs_num = ppi_regs_num << 1;
589 for (i = 0U; i < regs_num; ++i) {
590 SAVE_GICR_REG(gicr_base, rdist_ctx, icfgr, i);
591 }
592
593 rdist_ctx->gicr_nsacr = gicr_read_nsacr(gicr_base);
594
595 /* 4 interrupt IDs per GICR_IPRIORITYR register */
596 regs_num = ppi_regs_num << 3;
597 for (i = 0U; i < regs_num; ++i) {
Alexei Fedorovc7510c52020-04-07 18:16:18 +0100598 rdist_ctx->gicr_ipriorityr[i] =
599 gicr_ipriorityr_read(gicr_base, i);
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100600 }
Soby Mathew327548c2017-07-13 15:19:51 +0100601
602 /*
603 * Call the pre-save hook that implements the IMP DEF sequence that may
604 * be required on some GIC implementations. As this may need to access
605 * the Redistributor registers, we pass it proc_num.
606 */
607 gicv3_distif_pre_save(proc_num);
608}
609
610/*****************************************************************************
611 * Function to restore the GIC Redistributor register context. We disable
612 * LPI and per-cpu interrupts before we start restore of the Redistributor.
613 * This function must be invoked after Distributor restore but prior to
614 * CPU interface enable. The pending and active interrupts are restored
615 * after the interrupts are fully configured and enabled.
616 *****************************************************************************/
617void gicv3_rdistif_init_restore(unsigned int proc_num,
618 const gicv3_redist_ctx_t * const rdist_ctx)
619{
620 uintptr_t gicr_base;
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100621 unsigned int i, ppi_regs_num, regs_num;
Soby Mathew327548c2017-07-13 15:19:51 +0100622
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100623 assert(gicv3_driver_data != NULL);
Soby Mathew327548c2017-07-13 15:19:51 +0100624 assert(proc_num < gicv3_driver_data->rdistif_num);
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100625 assert(gicv3_driver_data->rdistif_base_addrs != NULL);
Soby Mathew327548c2017-07-13 15:19:51 +0100626 assert(IS_IN_EL3());
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100627 assert(rdist_ctx != NULL);
Soby Mathew327548c2017-07-13 15:19:51 +0100628
629 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
630
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100631#if GIC_EXT_INTID
632 /* Calculate number of PPI registers */
633 ppi_regs_num = (unsigned int)((gicr_read_typer(gicr_base) >>
634 TYPER_PPI_NUM_SHIFT) & TYPER_PPI_NUM_MASK) + 1;
635 /* All other values except PPInum [0-2] are reserved */
636 if (ppi_regs_num > 3U) {
637 ppi_regs_num = 1U;
638 }
639#else
640 ppi_regs_num = 1U;
641#endif
Soby Mathew327548c2017-07-13 15:19:51 +0100642 /* Power on redistributor */
643 gicv3_rdistif_on(proc_num);
644
645 /*
646 * Call the post-restore hook that implements the IMP DEF sequence that
647 * may be required on some GIC implementations. As this may need to
648 * access the Redistributor registers, we pass it proc_num.
649 */
650 gicv3_distif_post_restore(proc_num);
651
652 /*
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100653 * Disable all SGIs (imp. def.)/(E)PPIs before configuring them.
654 * This is a more scalable approach as it avoids clearing the enable
655 * bits in the GICD_CTLR.
Soby Mathew327548c2017-07-13 15:19:51 +0100656 */
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100657 for (i = 0U; i < ppi_regs_num; ++i) {
658 gicr_write_icenabler(gicr_base, i, ~0U);
659 }
660
Soby Mathew327548c2017-07-13 15:19:51 +0100661 /* Wait for pending writes to GICR_ICENABLER */
662 gicr_wait_for_pending_write(gicr_base);
663
664 /*
665 * Disable the LPIs to avoid unpredictable behavior when writing to
666 * GICR_PROPBASER and GICR_PENDBASER.
667 */
668 gicr_write_ctlr(gicr_base,
669 rdist_ctx->gicr_ctlr & ~(GICR_CTLR_EN_LPIS_BIT));
670
671 /* Restore registers' content */
672 gicr_write_propbaser(gicr_base, rdist_ctx->gicr_propbaser);
673 gicr_write_pendbaser(gicr_base, rdist_ctx->gicr_pendbaser);
674
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100675 /* 32 interrupt IDs per register */
676 for (i = 0U; i < ppi_regs_num; ++i) {
677 RESTORE_GICR_REG(gicr_base, rdist_ctx, igroupr, i);
678 RESTORE_GICR_REG(gicr_base, rdist_ctx, igrpmodr, i);
679 }
680
681 /* 4 interrupt IDs per GICR_IPRIORITYR register */
682 regs_num = ppi_regs_num << 3;
683 for (i = 0U; i < regs_num; ++i) {
Alexei Fedorovc7510c52020-04-07 18:16:18 +0100684 gicr_ipriorityr_write(gicr_base, i,
685 rdist_ctx->gicr_ipriorityr[i]);
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100686 }
Soby Mathew327548c2017-07-13 15:19:51 +0100687
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100688 /* 16 interrupt IDs per GICR_ICFGR register */
689 regs_num = ppi_regs_num << 1;
690 for (i = 0U; i < regs_num; ++i) {
691 RESTORE_GICR_REG(gicr_base, rdist_ctx, icfgr, i);
Soby Mathew327548c2017-07-13 15:19:51 +0100692 }
693
Soby Mathew327548c2017-07-13 15:19:51 +0100694 gicr_write_nsacr(gicr_base, rdist_ctx->gicr_nsacr);
695
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100696 /* Restore after group and priorities are set.
697 * 32 interrupt IDs per register
698 */
699 for (i = 0U; i < ppi_regs_num; ++i) {
700 RESTORE_GICR_REG(gicr_base, rdist_ctx, ispendr, i);
701 RESTORE_GICR_REG(gicr_base, rdist_ctx, isactiver, i);
702 }
Soby Mathew327548c2017-07-13 15:19:51 +0100703
704 /*
705 * Wait for all writes to the Distributor to complete before enabling
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100706 * the SGI and (E)PPIs.
Soby Mathew327548c2017-07-13 15:19:51 +0100707 */
708 gicr_wait_for_upstream_pending_write(gicr_base);
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100709
710 /* 32 interrupt IDs per GICR_ISENABLER register */
711 for (i = 0U; i < ppi_regs_num; ++i) {
712 RESTORE_GICR_REG(gicr_base, rdist_ctx, isenabler, i);
713 }
Soby Mathew327548c2017-07-13 15:19:51 +0100714
715 /*
716 * Restore GICR_CTLR.Enable_LPIs bit and wait for pending writes in case
717 * the first write to GICR_CTLR was still in flight (this write only
718 * restores GICR_CTLR.Enable_LPIs and no waiting is required for this
719 * bit).
720 */
721 gicr_write_ctlr(gicr_base, rdist_ctx->gicr_ctlr);
722 gicr_wait_for_pending_write(gicr_base);
723}
724
725/*****************************************************************************
726 * Function to save the GIC Distributor register context. This function
727 * must be invoked after CPU interface disable and Redistributor save.
728 *****************************************************************************/
729void gicv3_distif_save(gicv3_dist_ctx_t * const dist_ctx)
730{
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100731 unsigned int typer_reg, num_ints;
732#if GIC_EXT_INTID
733 unsigned int num_eints;
734#endif
Soby Mathew327548c2017-07-13 15:19:51 +0100735
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100736 assert(gicv3_driver_data != NULL);
737 assert(gicv3_driver_data->gicd_base != 0U);
Soby Mathew327548c2017-07-13 15:19:51 +0100738 assert(IS_IN_EL3());
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100739 assert(dist_ctx != NULL);
Soby Mathew327548c2017-07-13 15:19:51 +0100740
741 uintptr_t gicd_base = gicv3_driver_data->gicd_base;
742
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100743 typer_reg = gicd_read_typer(gicd_base);
744
745 /* Maximum SPI INTID is 32 * (GICD_TYPER.ITLinesNumber + 1) - 1 */
746 num_ints = ((typer_reg & TYPER_IT_LINES_NO_MASK) + 1U) << 5;
Soby Mathew327548c2017-07-13 15:19:51 +0100747
Alexei Fedorov68f26882019-09-13 15:47:13 +0100748 /* Filter out special INTIDs 1020-1023 */
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100749 if (num_ints > (MAX_SPI_ID + 1U)) {
Alexei Fedorov68f26882019-09-13 15:47:13 +0100750 num_ints = MAX_SPI_ID + 1U;
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100751 }
Soby Mathew327548c2017-07-13 15:19:51 +0100752
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100753#if GIC_EXT_INTID
754 /* Check if extended SPI range is implemented */
755 if ((typer_reg & TYPER_ESPI) != 0U) {
756 /*
757 * Maximum ESPI INTID is 32 * (GICD_TYPER.ESPI_range + 1) + 4095
758 */
759 num_eints = ((((typer_reg >> TYPER_ESPI_RANGE_SHIFT) &
Heyi Guoc5bd63c2020-05-19 14:01:49 +0800760 TYPER_ESPI_RANGE_MASK) + 1U) << 5) + MIN_ESPI_ID;
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100761 } else {
762 num_eints = 0U;
763 }
764#endif
Soby Mathew327548c2017-07-13 15:19:51 +0100765 /* Wait for pending write to complete */
766 gicd_wait_for_pending_write(gicd_base);
767
768 /* Save the GICD_CTLR */
769 dist_ctx->gicd_ctlr = gicd_read_ctlr(gicd_base);
770
Alexei Fedorov68f26882019-09-13 15:47:13 +0100771 /* Save GICD_IGROUPR for INTIDs 32 - 1019 */
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100772 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, igroupr, IGROUP);
773
774 /* Save GICD_IGROUPRE for INTIDs 4096 - 5119 */
775 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, igroupr, IGROUP);
Soby Mathew327548c2017-07-13 15:19:51 +0100776
Alexei Fedorov68f26882019-09-13 15:47:13 +0100777 /* Save GICD_ISENABLER for INT_IDs 32 - 1019 */
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100778 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, isenabler, ISENABLE);
779
780 /* Save GICD_ISENABLERE for INT_IDs 4096 - 5119 */
781 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, isenabler, ISENABLE);
Soby Mathew327548c2017-07-13 15:19:51 +0100782
Alexei Fedorov68f26882019-09-13 15:47:13 +0100783 /* Save GICD_ISPENDR for INTIDs 32 - 1019 */
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100784 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, ispendr, ISPEND);
785
786 /* Save GICD_ISPENDRE for INTIDs 4096 - 5119 */
787 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, ispendr, ISPEND);
Soby Mathew327548c2017-07-13 15:19:51 +0100788
Alexei Fedorov68f26882019-09-13 15:47:13 +0100789 /* Save GICD_ISACTIVER for INTIDs 32 - 1019 */
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100790 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, isactiver, ISACTIVE);
791
792 /* Save GICD_ISACTIVERE for INTIDs 4096 - 5119 */
793 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, isactiver, ISACTIVE);
Soby Mathew327548c2017-07-13 15:19:51 +0100794
Alexei Fedorov68f26882019-09-13 15:47:13 +0100795 /* Save GICD_IPRIORITYR for INTIDs 32 - 1019 */
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100796 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, ipriorityr, IPRIORITY);
797
798 /* Save GICD_IPRIORITYRE for INTIDs 4096 - 5119 */
799 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, ipriorityr, IPRIORITY);
Soby Mathew327548c2017-07-13 15:19:51 +0100800
Alexei Fedorov68f26882019-09-13 15:47:13 +0100801 /* Save GICD_ICFGR for INTIDs 32 - 1019 */
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100802 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, icfgr, ICFG);
803
804 /* Save GICD_ICFGRE for INTIDs 4096 - 5119 */
805 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, icfgr, ICFG);
Soby Mathew327548c2017-07-13 15:19:51 +0100806
Alexei Fedorov68f26882019-09-13 15:47:13 +0100807 /* Save GICD_IGRPMODR for INTIDs 32 - 1019 */
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100808 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, igrpmodr, IGRPMOD);
809
810 /* Save GICD_IGRPMODRE for INTIDs 4096 - 5119 */
811 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, igrpmodr, IGRPMOD);
Soby Mathew327548c2017-07-13 15:19:51 +0100812
Alexei Fedorov68f26882019-09-13 15:47:13 +0100813 /* Save GICD_NSACR for INTIDs 32 - 1019 */
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100814 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, nsacr, NSAC);
815
816 /* Save GICD_NSACRE for INTIDs 4096 - 5119 */
817 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, nsacr, NSAC);
Soby Mathew327548c2017-07-13 15:19:51 +0100818
Alexei Fedorov68f26882019-09-13 15:47:13 +0100819 /* Save GICD_IROUTER for INTIDs 32 - 1019 */
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100820 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, irouter, IROUTE);
821
822 /* Save GICD_IROUTERE for INTIDs 4096 - 5119 */
823 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, irouter, IROUTE);
Soby Mathew327548c2017-07-13 15:19:51 +0100824
825 /*
826 * GICD_ITARGETSR<n> and GICD_SPENDSGIR<n> are RAZ/WI when
827 * GICD_CTLR.ARE_(S|NS) bits are set which is the case for our GICv3
828 * driver.
829 */
830}
831
832/*****************************************************************************
833 * Function to restore the GIC Distributor register context. We disable G0, G1S
834 * and G1NS interrupt groups before we start restore of the Distributor. This
835 * function must be invoked prior to Redistributor restore and CPU interface
836 * enable. The pending and active interrupts are restored after the interrupts
837 * are fully configured and enabled.
838 *****************************************************************************/
839void gicv3_distif_init_restore(const gicv3_dist_ctx_t * const dist_ctx)
840{
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100841 unsigned int typer_reg, num_ints;
842#if GIC_EXT_INTID
843 unsigned int num_eints;
844#endif
Soby Mathew327548c2017-07-13 15:19:51 +0100845
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100846 assert(gicv3_driver_data != NULL);
847 assert(gicv3_driver_data->gicd_base != 0U);
Soby Mathew327548c2017-07-13 15:19:51 +0100848 assert(IS_IN_EL3());
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100849 assert(dist_ctx != NULL);
Soby Mathew327548c2017-07-13 15:19:51 +0100850
851 uintptr_t gicd_base = gicv3_driver_data->gicd_base;
852
853 /*
854 * Clear the "enable" bits for G0/G1S/G1NS interrupts before configuring
855 * the ARE_S bit. The Distributor might generate a system error
856 * otherwise.
857 */
858 gicd_clr_ctlr(gicd_base,
859 CTLR_ENABLE_G0_BIT |
860 CTLR_ENABLE_G1S_BIT |
861 CTLR_ENABLE_G1NS_BIT,
862 RWP_TRUE);
863
864 /* Set the ARE_S and ARE_NS bit now that interrupts have been disabled */
865 gicd_set_ctlr(gicd_base, CTLR_ARE_S_BIT | CTLR_ARE_NS_BIT, RWP_TRUE);
866
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100867 typer_reg = gicd_read_typer(gicd_base);
868
869 /* Maximum SPI INTID is 32 * (GICD_TYPER.ITLinesNumber + 1) - 1 */
870 num_ints = ((typer_reg & TYPER_IT_LINES_NO_MASK) + 1U) << 5;
Soby Mathew327548c2017-07-13 15:19:51 +0100871
Alexei Fedorov68f26882019-09-13 15:47:13 +0100872 /* Filter out special INTIDs 1020-1023 */
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100873 if (num_ints > (MAX_SPI_ID + 1U)) {
Alexei Fedorov68f26882019-09-13 15:47:13 +0100874 num_ints = MAX_SPI_ID + 1U;
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100875 }
Soby Mathew327548c2017-07-13 15:19:51 +0100876
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100877#if GIC_EXT_INTID
878 /* Check if extended SPI range is implemented */
879 if ((typer_reg & TYPER_ESPI) != 0U) {
880 /*
881 * Maximum ESPI INTID is 32 * (GICD_TYPER.ESPI_range + 1) + 4095
882 */
883 num_eints = ((((typer_reg >> TYPER_ESPI_RANGE_SHIFT) &
Heyi Guoc5bd63c2020-05-19 14:01:49 +0800884 TYPER_ESPI_RANGE_MASK) + 1U) << 5) + MIN_ESPI_ID;
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100885 } else {
886 num_eints = 0U;
887 }
888#endif
Alexei Fedorov68f26882019-09-13 15:47:13 +0100889 /* Restore GICD_IGROUPR for INTIDs 32 - 1019 */
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100890 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, igroupr, IGROUP);
891
892 /* Restore GICD_IGROUPRE for INTIDs 4096 - 5119 */
893 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, igroupr, IGROUP);
Soby Mathew327548c2017-07-13 15:19:51 +0100894
Alexei Fedorov68f26882019-09-13 15:47:13 +0100895 /* Restore GICD_IPRIORITYR for INTIDs 32 - 1019 */
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100896 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, ipriorityr, IPRIORITY);
897
898 /* Restore GICD_IPRIORITYRE for INTIDs 4096 - 5119 */
899 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, ipriorityr, IPRIORITY);
Soby Mathew327548c2017-07-13 15:19:51 +0100900
Alexei Fedorov68f26882019-09-13 15:47:13 +0100901 /* Restore GICD_ICFGR for INTIDs 32 - 1019 */
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100902 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, icfgr, ICFG);
903
904 /* Restore GICD_ICFGRE for INTIDs 4096 - 5119 */
905 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, icfgr, ICFG);
Soby Mathew327548c2017-07-13 15:19:51 +0100906
Alexei Fedorov68f26882019-09-13 15:47:13 +0100907 /* Restore GICD_IGRPMODR for INTIDs 32 - 1019 */
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100908 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, igrpmodr, IGRPMOD);
909
910 /* Restore GICD_IGRPMODRE for INTIDs 4096 - 5119 */
911 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, igrpmodr, IGRPMOD);
Soby Mathew327548c2017-07-13 15:19:51 +0100912
Alexei Fedorov68f26882019-09-13 15:47:13 +0100913 /* Restore GICD_NSACR for INTIDs 32 - 1019 */
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100914 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, nsacr, NSAC);
915
916 /* Restore GICD_NSACRE for INTIDs 4096 - 5119 */
917 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, nsacr, NSAC);
Soby Mathew327548c2017-07-13 15:19:51 +0100918
Alexei Fedorov68f26882019-09-13 15:47:13 +0100919 /* Restore GICD_IROUTER for INTIDs 32 - 1019 */
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100920 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, irouter, IROUTE);
921
922 /* Restore GICD_IROUTERE for INTIDs 4096 - 5119 */
923 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, irouter, IROUTE);
Soby Mathew327548c2017-07-13 15:19:51 +0100924
925 /*
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100926 * Restore ISENABLER(E), ISPENDR(E) and ISACTIVER(E) after
927 * the interrupts are configured.
Soby Mathew327548c2017-07-13 15:19:51 +0100928 */
929
Alexei Fedorov68f26882019-09-13 15:47:13 +0100930 /* Restore GICD_ISENABLER for INT_IDs 32 - 1019 */
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100931 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, isenabler, ISENABLE);
932
933 /* Restore GICD_ISENABLERE for INT_IDs 4096 - 5119 */
934 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, isenabler, ISENABLE);
Soby Mathew327548c2017-07-13 15:19:51 +0100935
Alexei Fedorov68f26882019-09-13 15:47:13 +0100936 /* Restore GICD_ISPENDR for INTIDs 32 - 1019 */
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100937 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, ispendr, ISPEND);
938
939 /* Restore GICD_ISPENDRE for INTIDs 4096 - 5119 */
940 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, ispendr, ISPEND);
Soby Mathew327548c2017-07-13 15:19:51 +0100941
Alexei Fedorov68f26882019-09-13 15:47:13 +0100942 /* Restore GICD_ISACTIVER for INTIDs 32 - 1019 */
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100943 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, isactiver, ISACTIVE);
944
945 /* Restore GICD_ISACTIVERE for INTIDs 4096 - 5119 */
946 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, isactiver, ISACTIVE);
Soby Mathew327548c2017-07-13 15:19:51 +0100947
948 /* Restore the GICD_CTLR */
949 gicd_write_ctlr(gicd_base, dist_ctx->gicd_ctlr);
950 gicd_wait_for_pending_write(gicd_base);
Soby Mathew327548c2017-07-13 15:19:51 +0100951}
Jeenu Viswambharanb1e957e2017-09-22 08:32:09 +0100952
953/*******************************************************************************
954 * This function gets the priority of the interrupt the processor is currently
955 * servicing.
956 ******************************************************************************/
957unsigned int gicv3_get_running_priority(void)
958{
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100959 return (unsigned int)read_icc_rpr_el1();
Jeenu Viswambharanb1e957e2017-09-22 08:32:09 +0100960}
Jeenu Viswambharan24e70292017-09-22 08:32:09 +0100961
962/*******************************************************************************
963 * This function checks if the interrupt identified by id is active (whether the
964 * state is either active, or active and pending). The proc_num is used if the
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100965 * interrupt is SGI or (E)PPI and programs the corresponding Redistributor
Jeenu Viswambharan24e70292017-09-22 08:32:09 +0100966 * interface.
967 ******************************************************************************/
968unsigned int gicv3_get_interrupt_active(unsigned int id, unsigned int proc_num)
969{
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100970 assert(gicv3_driver_data != NULL);
971 assert(gicv3_driver_data->gicd_base != 0U);
Jeenu Viswambharan24e70292017-09-22 08:32:09 +0100972 assert(proc_num < gicv3_driver_data->rdistif_num);
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100973 assert(gicv3_driver_data->rdistif_base_addrs != NULL);
Jeenu Viswambharan24e70292017-09-22 08:32:09 +0100974
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100975 /* Check interrupt ID */
976 if (is_sgi_ppi(id)) {
977 /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */
978 return gicr_get_isactiver(
979 gicv3_driver_data->rdistif_base_addrs[proc_num], id);
Jeenu Viswambharan24e70292017-09-22 08:32:09 +0100980 }
981
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100982 /* For SPIs: 32-1019 and ESPIs: 4096-5119 */
983 return gicd_get_isactiver(gicv3_driver_data->gicd_base, id);
Jeenu Viswambharan24e70292017-09-22 08:32:09 +0100984}
Jeenu Viswambharan0fcdfff2017-09-22 08:32:09 +0100985
986/*******************************************************************************
987 * This function enables the interrupt identified by id. The proc_num
988 * is used if the interrupt is SGI or PPI, and programs the corresponding
989 * Redistributor interface.
990 ******************************************************************************/
991void gicv3_enable_interrupt(unsigned int id, unsigned int proc_num)
992{
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100993 assert(gicv3_driver_data != NULL);
994 assert(gicv3_driver_data->gicd_base != 0U);
Jeenu Viswambharan0fcdfff2017-09-22 08:32:09 +0100995 assert(proc_num < gicv3_driver_data->rdistif_num);
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100996 assert(gicv3_driver_data->rdistif_base_addrs != NULL);
Jeenu Viswambharan0fcdfff2017-09-22 08:32:09 +0100997
998 /*
999 * Ensure that any shared variable updates depending on out of band
1000 * interrupt trigger are observed before enabling interrupt.
1001 */
1002 dsbishst();
Alexei Fedorova6e6ae02020-04-06 16:27:54 +01001003
1004 /* Check interrupt ID */
1005 if (is_sgi_ppi(id)) {
1006 /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */
1007 gicr_set_isenabler(
1008 gicv3_driver_data->rdistif_base_addrs[proc_num], id);
Jeenu Viswambharan0fcdfff2017-09-22 08:32:09 +01001009 } else {
Alexei Fedorova6e6ae02020-04-06 16:27:54 +01001010 /* For SPIs: 32-1019 and ESPIs: 4096-5119 */
Jeenu Viswambharan0fcdfff2017-09-22 08:32:09 +01001011 gicd_set_isenabler(gicv3_driver_data->gicd_base, id);
1012 }
1013}
1014
1015/*******************************************************************************
1016 * This function disables the interrupt identified by id. The proc_num
1017 * is used if the interrupt is SGI or PPI, and programs the corresponding
1018 * Redistributor interface.
1019 ******************************************************************************/
1020void gicv3_disable_interrupt(unsigned int id, unsigned int proc_num)
1021{
Antonio Nino Diazca994e72018-08-21 10:02:33 +01001022 assert(gicv3_driver_data != NULL);
1023 assert(gicv3_driver_data->gicd_base != 0U);
Jeenu Viswambharan0fcdfff2017-09-22 08:32:09 +01001024 assert(proc_num < gicv3_driver_data->rdistif_num);
Antonio Nino Diazca994e72018-08-21 10:02:33 +01001025 assert(gicv3_driver_data->rdistif_base_addrs != NULL);
Jeenu Viswambharan0fcdfff2017-09-22 08:32:09 +01001026
1027 /*
1028 * Disable interrupt, and ensure that any shared variable updates
1029 * depending on out of band interrupt trigger are observed afterwards.
1030 */
Alexei Fedorova6e6ae02020-04-06 16:27:54 +01001031
1032 /* Check interrupt ID */
1033 if (is_sgi_ppi(id)) {
1034 /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */
1035 gicr_set_icenabler(
1036 gicv3_driver_data->rdistif_base_addrs[proc_num], id);
Jeenu Viswambharan0fcdfff2017-09-22 08:32:09 +01001037
1038 /* Write to clear enable requires waiting for pending writes */
1039 gicr_wait_for_pending_write(
Alexei Fedorova6e6ae02020-04-06 16:27:54 +01001040 gicv3_driver_data->rdistif_base_addrs[proc_num]);
Jeenu Viswambharan0fcdfff2017-09-22 08:32:09 +01001041 } else {
Alexei Fedorova6e6ae02020-04-06 16:27:54 +01001042 /* For SPIs: 32-1019 and ESPIs: 4096-5119 */
Jeenu Viswambharan0fcdfff2017-09-22 08:32:09 +01001043 gicd_set_icenabler(gicv3_driver_data->gicd_base, id);
1044
1045 /* Write to clear enable requires waiting for pending writes */
1046 gicd_wait_for_pending_write(gicv3_driver_data->gicd_base);
1047 }
1048
1049 dsbishst();
1050}
Jeenu Viswambharan447b89d2017-09-22 08:32:09 +01001051
1052/*******************************************************************************
1053 * This function sets the interrupt priority as supplied for the given interrupt
1054 * id.
1055 ******************************************************************************/
1056void gicv3_set_interrupt_priority(unsigned int id, unsigned int proc_num,
1057 unsigned int priority)
1058{
1059 uintptr_t gicr_base;
1060
Antonio Nino Diazca994e72018-08-21 10:02:33 +01001061 assert(gicv3_driver_data != NULL);
1062 assert(gicv3_driver_data->gicd_base != 0U);
Jeenu Viswambharan447b89d2017-09-22 08:32:09 +01001063 assert(proc_num < gicv3_driver_data->rdistif_num);
Antonio Nino Diazca994e72018-08-21 10:02:33 +01001064 assert(gicv3_driver_data->rdistif_base_addrs != NULL);
Jeenu Viswambharan447b89d2017-09-22 08:32:09 +01001065
Alexei Fedorova6e6ae02020-04-06 16:27:54 +01001066 /* Check interrupt ID */
1067 if (is_sgi_ppi(id)) {
1068 /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */
Jeenu Viswambharan447b89d2017-09-22 08:32:09 +01001069 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
1070 gicr_set_ipriorityr(gicr_base, id, priority);
1071 } else {
Alexei Fedorova6e6ae02020-04-06 16:27:54 +01001072 /* For SPIs: 32-1019 and ESPIs: 4096-5119 */
Jeenu Viswambharan447b89d2017-09-22 08:32:09 +01001073 gicd_set_ipriorityr(gicv3_driver_data->gicd_base, id, priority);
1074 }
1075}
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +01001076
1077/*******************************************************************************
1078 * This function assigns group for the interrupt identified by id. The proc_num
Alexei Fedorova6e6ae02020-04-06 16:27:54 +01001079 * is used if the interrupt is SGI or (E)PPI, and programs the corresponding
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +01001080 * Redistributor interface. The group can be any of GICV3_INTR_GROUP*
1081 ******************************************************************************/
1082void gicv3_set_interrupt_type(unsigned int id, unsigned int proc_num,
1083 unsigned int type)
1084{
Antonio Nino Diazca994e72018-08-21 10:02:33 +01001085 bool igroup = false, grpmod = false;
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +01001086 uintptr_t gicr_base;
1087
Antonio Nino Diazca994e72018-08-21 10:02:33 +01001088 assert(gicv3_driver_data != NULL);
1089 assert(gicv3_driver_data->gicd_base != 0U);
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +01001090 assert(proc_num < gicv3_driver_data->rdistif_num);
Antonio Nino Diazca994e72018-08-21 10:02:33 +01001091 assert(gicv3_driver_data->rdistif_base_addrs != NULL);
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +01001092
1093 switch (type) {
1094 case INTR_GROUP1S:
Antonio Nino Diazca994e72018-08-21 10:02:33 +01001095 igroup = false;
1096 grpmod = true;
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +01001097 break;
1098 case INTR_GROUP0:
Antonio Nino Diazca994e72018-08-21 10:02:33 +01001099 igroup = false;
1100 grpmod = false;
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +01001101 break;
1102 case INTR_GROUP1NS:
Antonio Nino Diazca994e72018-08-21 10:02:33 +01001103 igroup = true;
1104 grpmod = false;
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +01001105 break;
1106 default:
Antonio Nino Diazca994e72018-08-21 10:02:33 +01001107 assert(false);
Jonathan Wright39b42212018-03-13 15:24:29 +00001108 break;
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +01001109 }
1110
Alexei Fedorova6e6ae02020-04-06 16:27:54 +01001111 /* Check interrupt ID */
1112 if (is_sgi_ppi(id)) {
1113 /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +01001114 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +01001115
Alexei Fedorova6e6ae02020-04-06 16:27:54 +01001116 igroup ? gicr_set_igroupr(gicr_base, id) :
1117 gicr_clr_igroupr(gicr_base, id);
1118 grpmod ? gicr_set_igrpmodr(gicr_base, id) :
1119 gicr_clr_igrpmodr(gicr_base, id);
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +01001120 } else {
Alexei Fedorova6e6ae02020-04-06 16:27:54 +01001121 /* For SPIs: 32-1019 and ESPIs: 4096-5119 */
1122
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +01001123 /* Serialize read-modify-write to Distributor registers */
1124 spin_lock(&gic_lock);
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +01001125
Alexei Fedorova6e6ae02020-04-06 16:27:54 +01001126 igroup ? gicd_set_igroupr(gicv3_driver_data->gicd_base, id) :
1127 gicd_clr_igroupr(gicv3_driver_data->gicd_base, id);
1128 grpmod ? gicd_set_igrpmodr(gicv3_driver_data->gicd_base, id) :
1129 gicd_clr_igrpmodr(gicv3_driver_data->gicd_base, id);
1130
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +01001131 spin_unlock(&gic_lock);
1132 }
1133}
Jeenu Viswambharanab14e9b2017-09-22 08:32:09 +01001134
1135/*******************************************************************************
1136 * This function raises the specified Secure Group 0 SGI.
1137 *
1138 * The target parameter must be a valid MPIDR in the system.
1139 ******************************************************************************/
Antonio Nino Diazca994e72018-08-21 10:02:33 +01001140void gicv3_raise_secure_g0_sgi(unsigned int sgi_num, u_register_t target)
Jeenu Viswambharanab14e9b2017-09-22 08:32:09 +01001141{
1142 unsigned int tgt, aff3, aff2, aff1, aff0;
1143 uint64_t sgi_val;
1144
1145 /* Verify interrupt number is in the SGI range */
1146 assert((sgi_num >= MIN_SGI_ID) && (sgi_num < MIN_PPI_ID));
1147
1148 /* Extract affinity fields from target */
1149 aff0 = MPIDR_AFFLVL0_VAL(target);
1150 aff1 = MPIDR_AFFLVL1_VAL(target);
1151 aff2 = MPIDR_AFFLVL2_VAL(target);
1152 aff3 = MPIDR_AFFLVL3_VAL(target);
1153
1154 /*
1155 * Make target list from affinity 0, and ensure GICv3 SGI can target
1156 * this PE.
1157 */
1158 assert(aff0 < GICV3_MAX_SGI_TARGETS);
Antonio Nino Diazca994e72018-08-21 10:02:33 +01001159 tgt = BIT_32(aff0);
Jeenu Viswambharanab14e9b2017-09-22 08:32:09 +01001160
1161 /* Raise SGI to PE specified by its affinity */
1162 sgi_val = GICV3_SGIR_VALUE(aff3, aff2, aff1, sgi_num, SGIR_IRM_TO_AFF,
1163 tgt);
1164
1165 /*
1166 * Ensure that any shared variable updates depending on out of band
1167 * interrupt trigger are observed before raising SGI.
1168 */
1169 dsbishst();
1170 write_icc_sgi0r_el1(sgi_val);
1171 isb();
1172}
Jeenu Viswambharandce70b32017-09-22 08:32:09 +01001173
1174/*******************************************************************************
Alexei Fedorova6e6ae02020-04-06 16:27:54 +01001175 * This function sets the interrupt routing for the given (E)SPI interrupt id.
Jeenu Viswambharandce70b32017-09-22 08:32:09 +01001176 * The interrupt routing is specified in routing mode and mpidr.
1177 *
1178 * The routing mode can be either of:
1179 * - GICV3_IRM_ANY
1180 * - GICV3_IRM_PE
1181 *
1182 * The mpidr is the affinity of the PE to which the interrupt will be routed,
1183 * and is ignored for routing mode GICV3_IRM_ANY.
1184 ******************************************************************************/
1185void gicv3_set_spi_routing(unsigned int id, unsigned int irm, u_register_t mpidr)
1186{
1187 unsigned long long aff;
1188 uint64_t router;
1189
Antonio Nino Diazca994e72018-08-21 10:02:33 +01001190 assert(gicv3_driver_data != NULL);
1191 assert(gicv3_driver_data->gicd_base != 0U);
Jeenu Viswambharandce70b32017-09-22 08:32:09 +01001192
1193 assert((irm == GICV3_IRM_ANY) || (irm == GICV3_IRM_PE));
Alexei Fedorova6e6ae02020-04-06 16:27:54 +01001194
1195 assert(IS_SPI(id));
Jeenu Viswambharandce70b32017-09-22 08:32:09 +01001196
1197 aff = gicd_irouter_val_from_mpidr(mpidr, irm);
1198 gicd_write_irouter(gicv3_driver_data->gicd_base, id, aff);
1199
1200 /*
1201 * In implementations that do not require 1 of N distribution of SPIs,
1202 * IRM might be RAZ/WI. Read back and verify IRM bit.
1203 */
1204 if (irm == GICV3_IRM_ANY) {
1205 router = gicd_read_irouter(gicv3_driver_data->gicd_base, id);
Antonio Nino Diazca994e72018-08-21 10:02:33 +01001206 if (((router >> IROUTER_IRM_SHIFT) & IROUTER_IRM_MASK) == 0U) {
Jeenu Viswambharandce70b32017-09-22 08:32:09 +01001207 ERROR("GICv3 implementation doesn't support routing ANY\n");
1208 panic();
1209 }
1210 }
1211}
Jeenu Viswambharaneb1c12c2017-09-22 08:32:09 +01001212
1213/*******************************************************************************
1214 * This function clears the pending status of an interrupt identified by id.
Alexei Fedorova6e6ae02020-04-06 16:27:54 +01001215 * The proc_num is used if the interrupt is SGI or (E)PPI, and programs the
Jeenu Viswambharaneb1c12c2017-09-22 08:32:09 +01001216 * corresponding Redistributor interface.
1217 ******************************************************************************/
1218void gicv3_clear_interrupt_pending(unsigned int id, unsigned int proc_num)
1219{
Antonio Nino Diazca994e72018-08-21 10:02:33 +01001220 assert(gicv3_driver_data != NULL);
1221 assert(gicv3_driver_data->gicd_base != 0U);
Jeenu Viswambharaneb1c12c2017-09-22 08:32:09 +01001222 assert(proc_num < gicv3_driver_data->rdistif_num);
Antonio Nino Diazca994e72018-08-21 10:02:33 +01001223 assert(gicv3_driver_data->rdistif_base_addrs != NULL);
Jeenu Viswambharaneb1c12c2017-09-22 08:32:09 +01001224
1225 /*
1226 * Clear pending interrupt, and ensure that any shared variable updates
1227 * depending on out of band interrupt trigger are observed afterwards.
1228 */
Alexei Fedorova6e6ae02020-04-06 16:27:54 +01001229
1230 /* Check interrupt ID */
1231 if (is_sgi_ppi(id)) {
1232 /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */
1233 gicr_set_icpendr(
1234 gicv3_driver_data->rdistif_base_addrs[proc_num], id);
Jeenu Viswambharaneb1c12c2017-09-22 08:32:09 +01001235 } else {
Alexei Fedorova6e6ae02020-04-06 16:27:54 +01001236 /* For SPIs: 32-1019 and ESPIs: 4096-5119 */
Jeenu Viswambharaneb1c12c2017-09-22 08:32:09 +01001237 gicd_set_icpendr(gicv3_driver_data->gicd_base, id);
1238 }
Alexei Fedorova6e6ae02020-04-06 16:27:54 +01001239
Jeenu Viswambharaneb1c12c2017-09-22 08:32:09 +01001240 dsbishst();
1241}
1242
1243/*******************************************************************************
1244 * This function sets the pending status of an interrupt identified by id.
1245 * The proc_num is used if the interrupt is SGI or PPI and programs the
1246 * corresponding Redistributor interface.
1247 ******************************************************************************/
1248void gicv3_set_interrupt_pending(unsigned int id, unsigned int proc_num)
1249{
Antonio Nino Diazca994e72018-08-21 10:02:33 +01001250 assert(gicv3_driver_data != NULL);
1251 assert(gicv3_driver_data->gicd_base != 0U);
Jeenu Viswambharaneb1c12c2017-09-22 08:32:09 +01001252 assert(proc_num < gicv3_driver_data->rdistif_num);
Antonio Nino Diazca994e72018-08-21 10:02:33 +01001253 assert(gicv3_driver_data->rdistif_base_addrs != NULL);
Jeenu Viswambharaneb1c12c2017-09-22 08:32:09 +01001254
1255 /*
1256 * Ensure that any shared variable updates depending on out of band
1257 * interrupt trigger are observed before setting interrupt pending.
1258 */
1259 dsbishst();
Alexei Fedorova6e6ae02020-04-06 16:27:54 +01001260
1261 /* Check interrupt ID */
1262 if (is_sgi_ppi(id)) {
1263 /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */
1264 gicr_set_ispendr(
1265 gicv3_driver_data->rdistif_base_addrs[proc_num], id);
Jeenu Viswambharaneb1c12c2017-09-22 08:32:09 +01001266 } else {
Alexei Fedorova6e6ae02020-04-06 16:27:54 +01001267 /* For SPIs: 32-1019 and ESPIs: 4096-5119 */
Jeenu Viswambharaneb1c12c2017-09-22 08:32:09 +01001268 gicd_set_ispendr(gicv3_driver_data->gicd_base, id);
1269 }
1270}
Jeenu Viswambharan62505072017-09-22 08:32:09 +01001271
1272/*******************************************************************************
1273 * This function sets the PMR register with the supplied value. Returns the
1274 * original PMR.
1275 ******************************************************************************/
1276unsigned int gicv3_set_pmr(unsigned int mask)
1277{
1278 unsigned int old_mask;
1279
Alexei Fedorova6e6ae02020-04-06 16:27:54 +01001280 old_mask = (unsigned int)read_icc_pmr_el1();
Jeenu Viswambharan62505072017-09-22 08:32:09 +01001281
1282 /*
1283 * Order memory updates w.r.t. PMR write, and ensure they're visible
1284 * before potential out of band interrupt trigger because of PMR update.
1285 * PMR system register writes are self-synchronizing, so no ISB required
1286 * thereafter.
1287 */
1288 dsbishst();
1289 write_icc_pmr_el1(mask);
1290
1291 return old_mask;
1292}
Madhukar Pappireddy5fd1f9d2019-05-15 18:25:41 -05001293
1294/*******************************************************************************
1295 * This function delegates the responsibility of discovering the corresponding
1296 * Redistributor frames to each CPU itself. It is a modified version of
1297 * gicv3_rdistif_base_addrs_probe() and is executed by each CPU in the platform
1298 * unlike the previous way in which only the Primary CPU did the discovery of
1299 * all the Redistributor frames for every CPU. It also handles the scenario in
1300 * which the frames of various CPUs are not contiguous in physical memory.
1301 ******************************************************************************/
1302int gicv3_rdistif_probe(const uintptr_t gicr_frame)
1303{
Heyi Guo3a579ae2020-05-19 11:50:40 +08001304 u_register_t mpidr, mpidr_self;
1305 unsigned int proc_num;
Madhukar Pappireddy5fd1f9d2019-05-15 18:25:41 -05001306 uint64_t typer_val;
1307 uintptr_t rdistif_base;
1308 bool gicr_frame_found = false;
1309
1310 assert(gicv3_driver_data->gicr_base == 0U);
1311
1312 /* Ensure this function is called with Data Cache enabled */
1313#ifndef __aarch64__
1314 assert((read_sctlr() & SCTLR_C_BIT) != 0U);
1315#else
1316 assert((read_sctlr_el3() & SCTLR_C_BIT) != 0U);
1317#endif /* !__aarch64__ */
1318
Heyi Guo3a579ae2020-05-19 11:50:40 +08001319 mpidr_self = read_mpidr_el1() & MPIDR_AFFINITY_MASK;
Madhukar Pappireddy5fd1f9d2019-05-15 18:25:41 -05001320 rdistif_base = gicr_frame;
1321 do {
1322 typer_val = gicr_read_typer(rdistif_base);
Heyi Guo3a579ae2020-05-19 11:50:40 +08001323 mpidr = mpidr_from_gicr_typer(typer_val);
Madhukar Pappireddy5fd1f9d2019-05-15 18:25:41 -05001324 if (gicv3_driver_data->mpidr_to_core_pos != NULL) {
Madhukar Pappireddy5fd1f9d2019-05-15 18:25:41 -05001325 proc_num = gicv3_driver_data->mpidr_to_core_pos(mpidr);
1326 } else {
Alexei Fedorova6e6ae02020-04-06 16:27:54 +01001327 proc_num = (unsigned int)(typer_val >>
1328 TYPER_PROC_NUM_SHIFT) & TYPER_PROC_NUM_MASK;
Madhukar Pappireddy5fd1f9d2019-05-15 18:25:41 -05001329 }
Heyi Guo3a579ae2020-05-19 11:50:40 +08001330 if (mpidr == mpidr_self) {
Madhukar Pappireddy5fd1f9d2019-05-15 18:25:41 -05001331 /* The base address doesn't need to be initialized on
1332 * every warm boot.
1333 */
Alexei Fedorova6e6ae02020-04-06 16:27:54 +01001334 if (gicv3_driver_data->rdistif_base_addrs[proc_num]
1335 != 0U) {
Madhukar Pappireddy5fd1f9d2019-05-15 18:25:41 -05001336 return 0;
Alexei Fedorova6e6ae02020-04-06 16:27:54 +01001337 }
Madhukar Pappireddy5fd1f9d2019-05-15 18:25:41 -05001338 gicv3_driver_data->rdistif_base_addrs[proc_num] =
1339 rdistif_base;
1340 gicr_frame_found = true;
1341 break;
1342 }
1343 rdistif_base += (uintptr_t)(ULL(1) << GICR_PCPUBASE_SHIFT);
1344 } while ((typer_val & TYPER_LAST_BIT) == 0U);
1345
Alexei Fedorova6e6ae02020-04-06 16:27:54 +01001346 if (!gicr_frame_found) {
Madhukar Pappireddy5fd1f9d2019-05-15 18:25:41 -05001347 return -1;
Alexei Fedorova6e6ae02020-04-06 16:27:54 +01001348 }
Madhukar Pappireddy5fd1f9d2019-05-15 18:25:41 -05001349
1350 /*
1351 * Flush the driver data to ensure coherency. This is
1352 * not required if platform has HW_ASSISTED_COHERENCY
1353 * enabled.
1354 */
1355#if !HW_ASSISTED_COHERENCY
1356 /*
1357 * Flush the rdistif_base_addrs[] contents linked to the GICv3 driver.
1358 */
1359 flush_dcache_range((uintptr_t)&(gicv3_driver_data->rdistif_base_addrs[proc_num]),
1360 sizeof(*(gicv3_driver_data->rdistif_base_addrs)));
1361#endif
1362 return 0; /* Found matching GICR frame */
1363}
Alexei Fedorova6e6ae02020-04-06 16:27:54 +01001364
1365/******************************************************************************
1366 * This function checks the interrupt ID and returns true for SGIs and (E)PPIs
1367 * and false for (E)SPIs IDs.
1368 *****************************************************************************/
1369static bool is_sgi_ppi(unsigned int id)
1370{
1371 /* SGIs: 0-15, PPIs: 16-31, EPPIs: 1056-1119 */
1372 if (IS_SGI_PPI(id)) {
1373 return true;
1374 }
1375
1376 /* SPIs: 32-1019, ESPIs: 4096-5119 */
1377 if (IS_SPI(id)) {
1378 return false;
1379 }
1380
1381 assert(false);
1382 panic();
1383}