Konstantin Porotchkin | ee4fa95 | 2018-10-08 16:50:54 +0300 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2016 Marvell International Ltd. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | * https://spdx.org/licenses |
| 6 | */ |
| 7 | |
| 8 | #ifndef __A3700_CONSOLE_H__ |
| 9 | #define __A3700_CONSOLE_H__ |
| 10 | |
| 11 | /* MVEBU UART Registers */ |
| 12 | #define UART_RX_REG 0x00 |
| 13 | #define UART_TX_REG 0x04 |
| 14 | #define UART_CTRL_REG 0x08 |
| 15 | #define UART_STATUS_REG 0x0c |
| 16 | #define UART_BAUD_REG 0x10 |
| 17 | #define UART_POSSR_REG 0x14 |
| 18 | |
| 19 | /* FIFO Control Register bits */ |
| 20 | #define UARTFCR_FIFOMD_16450 (0 << 6) |
| 21 | #define UARTFCR_FIFOMD_16550 (1 << 6) |
| 22 | #define UARTFCR_RXTRIG_1 (0 << 6) |
| 23 | #define UARTFCR_RXTRIG_4 (1 << 6) |
| 24 | #define UARTFCR_RXTRIG_8 (2 << 6) |
| 25 | #define UARTFCR_RXTRIG_16 (3 << 6) |
| 26 | #define UARTFCR_TXTRIG_1 (0 << 4) |
| 27 | #define UARTFCR_TXTRIG_4 (1 << 4) |
| 28 | #define UARTFCR_TXTRIG_8 (2 << 4) |
| 29 | #define UARTFCR_TXTRIG_16 (3 << 4) |
| 30 | #define UARTFCR_DMAEN (1 << 3) /* Enable DMA mode */ |
| 31 | #define UARTFCR_TXCLR (1 << 2) /* Clear contents of Tx FIFO */ |
| 32 | #define UARTFCR_RXCLR (1 << 1) /* Clear contents of Rx FIFO */ |
| 33 | #define UARTFCR_FIFOEN (1 << 0) /* Enable the Tx/Rx FIFO */ |
| 34 | |
| 35 | /* Line Control Register bits */ |
| 36 | #define UARTLCR_DLAB (1 << 7) /* Divisor Latch Access */ |
| 37 | #define UARTLCR_SETB (1 << 6) /* Set BREAK Condition */ |
| 38 | #define UARTLCR_SETP (1 << 5) /* Set Parity to LCR[4] */ |
| 39 | #define UARTLCR_EVEN (1 << 4) /* Even Parity Format */ |
| 40 | #define UARTLCR_PAR (1 << 3) /* Parity */ |
| 41 | #define UARTLCR_STOP (1 << 2) /* Stop Bit */ |
| 42 | #define UARTLCR_WORDSZ_5 0 /* Word Length of 5 */ |
| 43 | #define UARTLCR_WORDSZ_6 1 /* Word Length of 6 */ |
| 44 | #define UARTLCR_WORDSZ_7 2 /* Word Length of 7 */ |
| 45 | #define UARTLCR_WORDSZ_8 3 /* Word Length of 8 */ |
| 46 | |
| 47 | /* Line Status Register bits */ |
| 48 | #define UARTLSR_TXFIFOFULL (1 << 11) /* Tx Fifo Full */ |
| 49 | |
| 50 | /* UART Control Register bits */ |
| 51 | #define UART_CTRL_RXFIFO_RESET (1 << 14) |
| 52 | #define UART_CTRL_TXFIFO_RESET (1 << 15) |
| 53 | #define UARTLSR_TXFIFOEMPTY (1 << 6) |
| 54 | |
| 55 | #endif /* __A3700_CONSOLE_H__ */ |