Deepak Pandey | 9cbacf6 | 2018-08-08 10:32:51 +0530 | [diff] [blame] | 1 | /* |
Werner Lewis | f32d2ad | 2023-02-21 14:40:12 +0000 | [diff] [blame] | 2 | * Copyright (c) 2018-2023, Arm Limited. All rights reserved. |
Deepak Pandey | 9cbacf6 | 2018-08-08 10:32:51 +0530 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
Max Shvetsov | 0ac3941 | 2019-11-19 11:01:26 +0000 | [diff] [blame] | 7 | #include <common/debug.h> |
Antonio Nino Diaz | 1b0c6f1 | 2019-01-23 21:08:43 +0000 | [diff] [blame] | 8 | #include <drivers/arm/css/css_mhu_doorbell.h> |
Antonio Nino Diaz | c30db5b | 2019-01-23 20:37:32 +0000 | [diff] [blame] | 9 | #include <drivers/arm/css/scmi.h> |
Manoj Kumar | 69bebd8 | 2019-06-21 17:07:13 +0100 | [diff] [blame] | 10 | #include <drivers/arm/css/sds.h> |
Manish Pandey | 2c44a44 | 2019-10-14 17:37:38 +0100 | [diff] [blame] | 11 | #include <drivers/arm/gic600_multichip.h> |
Manoj Kumar | 69bebd8 | 2019-06-21 17:07:13 +0100 | [diff] [blame] | 12 | #include <lib/mmio.h> |
| 13 | #include <lib/utils.h> |
Antonio Nino Diaz | bd7b740 | 2019-01-25 14:30:04 +0000 | [diff] [blame] | 14 | #include <plat/arm/common/plat_arm.h> |
| 15 | |
Manoj Kumar | 69bebd8 | 2019-06-21 17:07:13 +0100 | [diff] [blame] | 16 | #include "n1sdp_def.h" |
Werner Lewis | f32d2ad | 2023-02-21 14:40:12 +0000 | [diff] [blame] | 17 | #include "n1sdp_private.h" |
sah01 | 6ec01e8 | 2021-06-06 14:38:01 +0530 | [diff] [blame] | 18 | #include <platform_def.h> |
Manoj Kumar | 69bebd8 | 2019-06-21 17:07:13 +0100 | [diff] [blame] | 19 | |
| 20 | /* |
Manish Pandey | 2f3203f | 2019-10-07 17:47:46 +0100 | [diff] [blame] | 21 | * Platform information structure stored in SDS. |
| 22 | * This structure holds information about platform's DDR |
| 23 | * size which will be used to zero out the memory before |
| 24 | * enabling the ECC capability as well as information |
| 25 | * about multichip setup |
| 26 | * - multichip mode |
sah01 | 6ec01e8 | 2021-06-06 14:38:01 +0530 | [diff] [blame] | 27 | * - secondary_count |
Manish Pandey | 2f3203f | 2019-10-07 17:47:46 +0100 | [diff] [blame] | 28 | * - Local DDR size in GB, DDR memory in master board |
sah01 | 6ec01e8 | 2021-06-06 14:38:01 +0530 | [diff] [blame] | 29 | * - Remote DDR size in GB, DDR memory in secondary board |
Manoj Kumar | 69bebd8 | 2019-06-21 17:07:13 +0100 | [diff] [blame] | 30 | */ |
Manish Pandey | 2f3203f | 2019-10-07 17:47:46 +0100 | [diff] [blame] | 31 | struct n1sdp_plat_info { |
| 32 | bool multichip_mode; |
sah01 | 6ec01e8 | 2021-06-06 14:38:01 +0530 | [diff] [blame] | 33 | uint8_t secondary_count; |
Manish Pandey | 2f3203f | 2019-10-07 17:47:46 +0100 | [diff] [blame] | 34 | uint8_t local_ddr_size; |
| 35 | uint8_t remote_ddr_size; |
| 36 | } __packed; |
Manoj Kumar | 69bebd8 | 2019-06-21 17:07:13 +0100 | [diff] [blame] | 37 | |
Deepak Pandey | 9cbacf6 | 2018-08-08 10:32:51 +0530 | [diff] [blame] | 38 | static scmi_channel_plat_info_t n1sdp_scmi_plat_info = { |
Manish Pandey | 2f3203f | 2019-10-07 17:47:46 +0100 | [diff] [blame] | 39 | .scmi_mbx_mem = N1SDP_SCMI_PAYLOAD_BASE, |
| 40 | .db_reg_addr = PLAT_CSS_MHU_BASE + CSS_SCMI_MHU_DB_REG_OFF, |
| 41 | .db_preserve_mask = 0xfffffffe, |
| 42 | .db_modify_mask = 0x1, |
| 43 | .ring_doorbell = &mhu_ring_doorbell |
Deepak Pandey | 9cbacf6 | 2018-08-08 10:32:51 +0530 | [diff] [blame] | 44 | }; |
| 45 | |
Manish Pandey | 2c44a44 | 2019-10-14 17:37:38 +0100 | [diff] [blame] | 46 | static struct gic600_multichip_data n1sdp_multichip_data __init = { |
| 47 | .rt_owner_base = PLAT_ARM_GICD_BASE, |
| 48 | .rt_owner = 0, |
| 49 | .chip_count = 1, |
| 50 | .chip_addrs = { |
| 51 | PLAT_ARM_GICD_BASE >> 16, |
| 52 | PLAT_ARM_GICD_BASE >> 16 |
| 53 | }, |
| 54 | .spi_ids = { |
sahil | 799c13f | 2023-06-06 11:30:14 +0530 | [diff] [blame^] | 55 | {PLAT_ARM_GICD_BASE, 32, 511}, |
| 56 | {PLAT_ARM_GICD_BASE, 512, 991} |
Manish Pandey | 2c44a44 | 2019-10-14 17:37:38 +0100 | [diff] [blame] | 57 | } |
| 58 | }; |
| 59 | |
| 60 | static uintptr_t n1sdp_multichip_gicr_frames[3] = { |
| 61 | PLAT_ARM_GICR_BASE, |
| 62 | PLAT_ARM_GICR_BASE + PLAT_ARM_REMOTE_CHIP_OFFSET, |
| 63 | 0 |
| 64 | }; |
| 65 | |
Tony K Nadackal | 1b116a8 | 2022-12-07 20:44:05 +0000 | [diff] [blame] | 66 | scmi_channel_plat_info_t *plat_css_get_scmi_info(unsigned int channel_id) |
Deepak Pandey | 9cbacf6 | 2018-08-08 10:32:51 +0530 | [diff] [blame] | 67 | { |
| 68 | return &n1sdp_scmi_plat_info; |
| 69 | } |
Chandni Cherukuri | e4bf6a0 | 2018-11-14 13:43:59 +0530 | [diff] [blame] | 70 | |
| 71 | const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops) |
| 72 | { |
Werner Lewis | f32d2ad | 2023-02-21 14:40:12 +0000 | [diff] [blame] | 73 | ops->pwr_domain_off = n1sdp_pwr_domain_off; |
Chandni Cherukuri | e4bf6a0 | 2018-11-14 13:43:59 +0530 | [diff] [blame] | 74 | return css_scmi_override_pm_ops(ops); |
| 75 | } |
Manoj Kumar | 69bebd8 | 2019-06-21 17:07:13 +0100 | [diff] [blame] | 76 | |
| 77 | /* |
| 78 | * N1SDP platform supports RDIMMs with ECC capability. To use the ECC |
| 79 | * capability, the entire DDR memory space has to be zeroed out before |
| 80 | * enabling the ECC bits in DMC620. Zeroing out several gigabytes of |
| 81 | * memory from SCP is quite time consuming so the following function |
| 82 | * is added to zero out the DDR memory from application processor which is |
sah01 | 6ec01e8 | 2021-06-06 14:38:01 +0530 | [diff] [blame] | 83 | * much faster compared to SCP. Local DDR memory is zeroed out during BL2 |
| 84 | * stage. If remote chip is connected, it's DDR memory is zeroed out here. |
Manoj Kumar | 69bebd8 | 2019-06-21 17:07:13 +0100 | [diff] [blame] | 85 | */ |
| 86 | |
Manish Pandey | b68e286 | 2019-09-11 17:07:40 +0100 | [diff] [blame] | 87 | void remote_dmc_ecc_setup(uint8_t remote_ddr_size) |
| 88 | { |
| 89 | uint64_t remote_dram2_size; |
| 90 | |
| 91 | remote_dram2_size = (remote_ddr_size * 1024UL * 1024UL * 1024UL) - |
| 92 | N1SDP_REMOTE_DRAM1_SIZE; |
| 93 | /* multichip setup */ |
| 94 | INFO("Zeroing remote DDR memories\n"); |
| 95 | zero_normalmem((void *)N1SDP_REMOTE_DRAM1_BASE, |
| 96 | N1SDP_REMOTE_DRAM1_SIZE); |
| 97 | flush_dcache_range(N1SDP_REMOTE_DRAM1_BASE, N1SDP_REMOTE_DRAM1_SIZE); |
| 98 | zero_normalmem((void *)N1SDP_REMOTE_DRAM2_BASE, remote_dram2_size); |
| 99 | flush_dcache_range(N1SDP_REMOTE_DRAM2_BASE, remote_dram2_size); |
| 100 | |
| 101 | INFO("Enabling ECC on remote DMCs\n"); |
| 102 | /* Set DMCs to CONFIG state before writing ERR0CTLR0 register */ |
| 103 | mmio_write_32(N1SDP_REMOTE_DMC0_MEMC_CMD_REG, |
| 104 | N1SDP_DMC_MEMC_CMD_CONFIG); |
| 105 | mmio_write_32(N1SDP_REMOTE_DMC1_MEMC_CMD_REG, |
| 106 | N1SDP_DMC_MEMC_CMD_CONFIG); |
| 107 | |
| 108 | /* Enable ECC in DMCs */ |
| 109 | mmio_setbits_32(N1SDP_REMOTE_DMC0_ERR0CTLR0_REG, |
| 110 | N1SDP_DMC_ERR0CTLR0_ECC_EN); |
| 111 | mmio_setbits_32(N1SDP_REMOTE_DMC1_ERR0CTLR0_REG, |
| 112 | N1SDP_DMC_ERR0CTLR0_ECC_EN); |
| 113 | |
| 114 | /* Set DMCs to READY state */ |
| 115 | mmio_write_32(N1SDP_REMOTE_DMC0_MEMC_CMD_REG, N1SDP_DMC_MEMC_CMD_READY); |
| 116 | mmio_write_32(N1SDP_REMOTE_DMC1_MEMC_CMD_REG, N1SDP_DMC_MEMC_CMD_READY); |
| 117 | } |
| 118 | |
Manish Pandey | 2c44a44 | 2019-10-14 17:37:38 +0100 | [diff] [blame] | 119 | void n1sdp_bl31_multichip_setup(void) |
| 120 | { |
| 121 | plat_arm_override_gicr_frames(n1sdp_multichip_gicr_frames); |
| 122 | gic600_multichip_init(&n1sdp_multichip_data); |
| 123 | } |
| 124 | |
Manoj Kumar | 69bebd8 | 2019-06-21 17:07:13 +0100 | [diff] [blame] | 125 | void bl31_platform_setup(void) |
| 126 | { |
| 127 | int ret; |
Manish Pandey | 2f3203f | 2019-10-07 17:47:46 +0100 | [diff] [blame] | 128 | struct n1sdp_plat_info plat_info; |
Manoj Kumar | 69bebd8 | 2019-06-21 17:07:13 +0100 | [diff] [blame] | 129 | |
Manoj Kumar | 69bebd8 | 2019-06-21 17:07:13 +0100 | [diff] [blame] | 130 | ret = sds_init(); |
| 131 | if (ret != SDS_OK) { |
| 132 | ERROR("SDS initialization failed\n"); |
| 133 | panic(); |
| 134 | } |
| 135 | |
Manish Pandey | 2f3203f | 2019-10-07 17:47:46 +0100 | [diff] [blame] | 136 | ret = sds_struct_read(N1SDP_SDS_PLATFORM_INFO_STRUCT_ID, |
| 137 | N1SDP_SDS_PLATFORM_INFO_OFFSET, |
| 138 | &plat_info, |
| 139 | N1SDP_SDS_PLATFORM_INFO_SIZE, |
Manoj Kumar | 69bebd8 | 2019-06-21 17:07:13 +0100 | [diff] [blame] | 140 | SDS_ACCESS_MODE_NON_CACHED); |
| 141 | if (ret != SDS_OK) { |
Manish Pandey | 2f3203f | 2019-10-07 17:47:46 +0100 | [diff] [blame] | 142 | ERROR("Error getting platform info from SDS\n"); |
| 143 | panic(); |
| 144 | } |
| 145 | /* Validate plat_info SDS */ |
| 146 | if ((plat_info.local_ddr_size == 0) |
| 147 | || (plat_info.local_ddr_size > N1SDP_MAX_DDR_CAPACITY_GB) |
| 148 | || (plat_info.remote_ddr_size > N1SDP_MAX_DDR_CAPACITY_GB) |
sah01 | 6ec01e8 | 2021-06-06 14:38:01 +0530 | [diff] [blame] | 149 | || (plat_info.secondary_count > N1SDP_MAX_SECONDARY_COUNT)) { |
Manish Pandey | 2f3203f | 2019-10-07 17:47:46 +0100 | [diff] [blame] | 150 | ERROR("platform info SDS is corrupted\n"); |
Manoj Kumar | 69bebd8 | 2019-06-21 17:07:13 +0100 | [diff] [blame] | 151 | panic(); |
| 152 | } |
Manish Pandey | 2f3203f | 2019-10-07 17:47:46 +0100 | [diff] [blame] | 153 | |
Manish Pandey | 2c44a44 | 2019-10-14 17:37:38 +0100 | [diff] [blame] | 154 | if (plat_info.multichip_mode) { |
sah01 | 6ec01e8 | 2021-06-06 14:38:01 +0530 | [diff] [blame] | 155 | n1sdp_multichip_data.chip_count = plat_info.secondary_count + 1; |
Manish Pandey | 2c44a44 | 2019-10-14 17:37:38 +0100 | [diff] [blame] | 156 | n1sdp_bl31_multichip_setup(); |
| 157 | } |
| 158 | arm_bl31_platform_setup(); |
| 159 | |
Manish Pandey | b68e286 | 2019-09-11 17:07:40 +0100 | [diff] [blame] | 160 | /* Check if remote memory is present */ |
| 161 | if ((plat_info.multichip_mode) && (plat_info.remote_ddr_size != 0)) |
| 162 | remote_dmc_ecc_setup(plat_info.remote_ddr_size); |
Manoj Kumar | 69bebd8 | 2019-06-21 17:07:13 +0100 | [diff] [blame] | 163 | } |
Madhukar Pappireddy | 042043b | 2023-03-02 16:33:25 -0600 | [diff] [blame] | 164 | |
Govindraj Raja | 436ea5e | 2023-05-10 14:50:36 -0500 | [diff] [blame] | 165 | #if defined(SPD_spmd) && (SPMC_AT_EL3 == 0) |
Madhukar Pappireddy | 042043b | 2023-03-02 16:33:25 -0600 | [diff] [blame] | 166 | /* |
| 167 | * A dummy implementation of the platform handler for Group0 secure interrupt. |
| 168 | */ |
| 169 | int plat_spmd_handle_group0_interrupt(uint32_t intid) |
| 170 | { |
| 171 | (void)intid; |
| 172 | return -1; |
| 173 | } |
Govindraj Raja | 436ea5e | 2023-05-10 14:50:36 -0500 | [diff] [blame] | 174 | #endif /*defined(SPD_spmd) && (SPMC_AT_EL3 == 0)*/ |