blob: 91212e8a056a16c97a0b2c01ec2908544516aff7 [file] [log] [blame]
Usama Arif82e95092019-06-18 16:46:05 +01001/*
2 * Copyright (c) 2019, Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7/dts-v1/;
8
9/ {
10 model = "A5DS";
11 compatible = "arm,A5DS";
12 interrupt-parent = <&gic>;
13 #address-cells = <1>;
14 #size-cells = <1>;
Usama Arif79913a82019-09-19 11:07:24 +010015
16 psci {
17 compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
18 method = "smc";
19 cpu_on = <0x84000003>;
20 };
21
Usama Arif82e95092019-06-18 16:46:05 +010022 cpus {
23 #address-cells = <1>;
24 #size-cells = <0>;
25 cpu@0 {
26 device_type = "cpu";
27 compatible = "arm,cortex-a5";
Usama Arif79913a82019-09-19 11:07:24 +010028 enable-method = "psci";
Usama Arif82e95092019-06-18 16:46:05 +010029 reg = <0>;
30 };
Usama Arif79913a82019-09-19 11:07:24 +010031 cpu@1 {
32 device_type = "cpu";
33 compatible = "arm,cortex-a5";
34 enable-method = "psci";
35 reg = <1>;
36 };
37 cpu@2 {
38 device_type = "cpu";
39 compatible = "arm,cortex-a5";
40 enable-method = "psci";
41 reg = <2>;
42 };
43 cpu@3 {
44 device_type = "cpu";
45 compatible = "arm,cortex-a5";
46 enable-method = "psci";
47 reg = <3>;
48 };
Usama Arif82e95092019-06-18 16:46:05 +010049 };
50
51 memory@80000000 {
52 device_type = "memory";
53 reg = <0x80000000 0x7F000000>;
54 };
55
56 refclk100mhz: refclk100mhz {
57 compatible = "fixed-clock";
58 #clock-cells = <0>;
59 clock-frequency = <100000000>;
60 clock-output-names = "apb_pclk";
61 };
62
63 smbclk: refclk24mhzx2 {
64 compatible = "fixed-clock";
65 #clock-cells = <0>;
66 clock-frequency = <48000000>;
67 clock-output-names = "smclk";
68 };
69
70
71 rtc@1a220000 {
72 compatible = "arm,pl031", "arm,primecell";
73 reg = <0x1a220000 0x1000>;
74 clocks = <&refclk100mhz>;
75 interrupts = <0 6 0xf04>;
76 clock-names = "apb_pclk";
77 };
78
79 gic: interrupt-controller@1c001000 {
80 compatible = "arm,cortex-a9-gic";
81 #interrupt-cells = <3>;
82 #address-cells = <0>;
83 interrupt-controller;
84 reg = <0x1c001000 0x1000>,
85 <0x1c000100 0x100>;
86 interrupts = <1 9 0xf04>;
87 };
88
89 serial0: uart@1a200000 {
90 compatible = "arm,pl011", "arm,primecell";
91 reg = <0x1a200000 0x1000>;
92 interrupt-parent = <&gic>;
93 interrupts = <0 8 0xf04>;
94 clocks = <&refclk100mhz>;
95 clock-names = "apb_pclk";
96 };
97
98 serial1: uart@1a210000 {
99 compatible = "arm,pl011", "arm,primecell";
100 reg = <0x1a210000 0x1000>;
101 interrupt-parent = <&gic>;
102 interrupts = <0 9 0xf04>;
103 clocks = <&refclk100mhz>;
104 clock-names = "apb_pclk";
105 };
106
107 timer0: timer@1a040000 {
108 compatible = "arm,armv7-timer-mem";
109 #address-cells = <1>;
110 #size-cells = <1>;
111 ranges;
112 reg = <0x1a040000 0x1000>;
113 clock-frequency = <50000000>;
114
115 frame@1a050000 {
116 frame-number = <0>;
117 interrupts = <0 2 0xf04>;
118 reg = <0x1a050000 0x1000>;
119 };
120 };
121};