| johpow01 | a3810e8 | 2021-05-18 15:23:31 -0500 | [diff] [blame] | 1 | /* |
| Bipin Ravi | 8649974 | 2022-01-18 01:59:06 -0600 | [diff] [blame] | 2 | * Copyright (c) 2021-2022, Arm Limited. All rights reserved. |
| johpow01 | a3810e8 | 2021-05-18 15:23:31 -0500 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef CORTEX_A710_H |
| 8 | #define CORTEX_A710_H |
| 9 | |
| 10 | #define CORTEX_A710_MIDR U(0x410FD470) |
| 11 | |
| Bipin Ravi | 8649974 | 2022-01-18 01:59:06 -0600 | [diff] [blame] | 12 | /* Cortex-A710 loop count for CVE-2022-23960 mitigation */ |
| 13 | #define CORTEX_A710_BHB_LOOP_COUNT U(32) |
| 14 | |
| johpow01 | a3810e8 | 2021-05-18 15:23:31 -0500 | [diff] [blame] | 15 | /******************************************************************************* |
| 16 | * CPU Extended Control register specific definitions |
| 17 | ******************************************************************************/ |
| 18 | #define CORTEX_A710_CPUECTLR_EL1 S3_0_C15_C1_4 |
| nayanpatel-arm | 0b338b4 | 2021-09-16 15:27:53 -0700 | [diff] [blame] | 19 | #define CORTEX_A710_CPUECTLR_EL1_PFSTIDIS_BIT (ULL(1) << 8) |
| johpow01 | a3810e8 | 2021-05-18 15:23:31 -0500 | [diff] [blame] | 20 | |
| 21 | /******************************************************************************* |
| 22 | * CPU Power Control register specific definitions |
| 23 | ******************************************************************************/ |
| 24 | #define CORTEX_A710_CPUPWRCTLR_EL1 S3_0_C15_C2_7 |
| 25 | #define CORTEX_A710_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) |
| 26 | |
| Bipin Ravi | cd39b14 | 2021-03-31 16:45:40 -0500 | [diff] [blame] | 27 | /******************************************************************************* |
| 28 | * CPU Auxiliary Control register specific definitions. |
| 29 | ******************************************************************************/ |
| 30 | #define CORTEX_A710_CPUACTLR_EL1 S3_0_C15_C1_0 |
| nayanpatel-arm | f2dce0e | 2021-09-22 12:35:03 -0700 | [diff] [blame] | 31 | #define CORTEX_A710_CPUACTLR_EL1_BIT_46 (ULL(1) << 46) |
| Bipin Ravi | 32705b1 | 2022-02-06 02:32:54 -0600 | [diff] [blame] | 32 | #define CORTEX_A710_CPUACTLR_EL1_BIT_22 (ULL(1) << 22) |
| nayanpatel-arm | 0b338b4 | 2021-09-16 15:27:53 -0700 | [diff] [blame] | 33 | |
| 34 | /******************************************************************************* |
| johpow01 | 7249fd0 | 2022-02-28 18:34:04 -0600 | [diff] [blame] | 35 | * CPU Auxiliary Control register 2 specific definitions. |
| 36 | ******************************************************************************/ |
| 37 | #define CORTEX_A710_CPUACTLR2_EL1 S3_0_C15_C1_1 |
| Bipin Ravi | 77eab29 | 2022-07-12 15:53:21 -0500 | [diff] [blame] | 38 | #define CORTEX_A710_CPUACTLR2_EL1_BIT_40 (ULL(1) << 40) |
| johpow01 | 7249fd0 | 2022-02-28 18:34:04 -0600 | [diff] [blame] | 39 | |
| 40 | /******************************************************************************* |
| 41 | * CPU Auxiliary Control register 5 specific definitions. |
| nayanpatel-arm | 0b338b4 | 2021-09-16 15:27:53 -0700 | [diff] [blame] | 42 | ******************************************************************************/ |
| 43 | #define CORTEX_A710_CPUACTLR5_EL1 S3_0_C15_C8_0 |
| 44 | #define CORTEX_A710_CPUACTLR5_EL1_BIT_13 (ULL(1) << 13) |
| Jayanth Dodderi Chidanand | de4f589 | 2022-09-01 22:09:54 +0100 | [diff] [blame] | 45 | #define CORTEX_A710_CPUACTLR5_EL1_BIT_17 (ULL(1) << 17) |
| Bipin Ravi | d53069b | 2022-02-06 03:11:44 -0600 | [diff] [blame] | 46 | #define CORTEX_A710_CPUACTLR5_EL1_BIT_44 (ULL(1) << 44) |
| Bipin Ravi | cd39b14 | 2021-03-31 16:45:40 -0500 | [diff] [blame] | 47 | |
| nayanpatel-arm | f2dce0e | 2021-09-22 12:35:03 -0700 | [diff] [blame] | 48 | /******************************************************************************* |
| 49 | * CPU Auxiliary Control register specific definitions. |
| 50 | ******************************************************************************/ |
| 51 | #define CORTEX_A710_CPUECTLR2_EL1 S3_0_C15_C1_5 |
| 52 | #define CORTEX_A710_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(9) |
| 53 | #define CPUECTLR2_EL1_PF_MODE_LSB U(11) |
| 54 | #define CPUECTLR2_EL1_PF_MODE_WIDTH U(4) |
| 55 | |
| Jayanth Dodderi Chidanand | de4f589 | 2022-09-01 22:09:54 +0100 | [diff] [blame] | 56 | /******************************************************************************* |
| 57 | * CPU Selected Instruction Private register specific definitions. |
| 58 | ******************************************************************************/ |
| 59 | #define CORTEX_A710_CPUPSELR_EL3 S3_6_C15_C8_0 |
| 60 | #define CORTEX_A710_CPUPCR_EL3 S3_6_C15_C8_1 |
| 61 | #define CORTEX_A710_CPUPOR_EL3 S3_6_C15_C8_2 |
| 62 | #define CORTEX_A710_CPUPMR_EL3 S3_6_C15_C8_3 |
| 63 | |
| johpow01 | a3810e8 | 2021-05-18 15:23:31 -0500 | [diff] [blame] | 64 | #endif /* CORTEX_A710_H */ |