Sheetal Tigadoli | 13680c9 | 2019-12-13 10:39:06 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2015-2020, Broadcom |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef PLATFORM_DEF_H |
| 8 | #define PLATFORM_DEF_H |
| 9 | |
| 10 | #include <arch.h> |
| 11 | #include <common/tbbr/tbbr_img_def.h> |
| 12 | #include <plat/common/common_def.h> |
| 13 | |
| 14 | #include <brcm_def.h> |
Sheetal Tigadoli | 13680c9 | 2019-12-13 10:39:06 +0530 | [diff] [blame] | 15 | #include "sr_def.h" |
Sheetal Tigadoli | ad0943e | 2019-12-18 19:44:43 +0530 | [diff] [blame] | 16 | #include <cmn_plat_def.h> |
Sheetal Tigadoli | 13680c9 | 2019-12-13 10:39:06 +0530 | [diff] [blame] | 17 | |
| 18 | /* |
| 19 | * Most platform porting definitions provided by included headers |
| 20 | */ |
| 21 | #define PLAT_BRCM_SCP_TZC_DRAM1_SIZE ULL(0x0) |
| 22 | |
| 23 | /* |
| 24 | * Required by standard platform porting definitions |
| 25 | */ |
| 26 | #define PLATFORM_CLUSTER0_CORE_COUNT 2 |
| 27 | #define PLATFORM_CLUSTER1_CORE_COUNT 2 |
| 28 | #define PLATFORM_CLUSTER2_CORE_COUNT 2 |
| 29 | #define PLATFORM_CLUSTER3_CORE_COUNT 2 |
Sheetal Tigadoli | 13680c9 | 2019-12-13 10:39:06 +0530 | [diff] [blame] | 30 | |
| 31 | #define BRCM_SYSTEM_COUNT 1 |
Sheetal Tigadoli | 2a96dc2 | 2019-12-18 12:01:01 +0530 | [diff] [blame] | 32 | #define BRCM_CLUSTER_COUNT 4 |
Sheetal Tigadoli | 13680c9 | 2019-12-13 10:39:06 +0530 | [diff] [blame] | 33 | |
| 34 | #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT + \ |
| 35 | PLATFORM_CLUSTER1_CORE_COUNT+ \ |
| 36 | PLATFORM_CLUSTER2_CORE_COUNT+ \ |
Sheetal Tigadoli | 2a96dc2 | 2019-12-18 12:01:01 +0530 | [diff] [blame] | 37 | PLATFORM_CLUSTER3_CORE_COUNT) |
Sheetal Tigadoli | 13680c9 | 2019-12-13 10:39:06 +0530 | [diff] [blame] | 38 | |
| 39 | #define PLAT_NUM_PWR_DOMAINS (BRCM_SYSTEM_COUNT + \ |
| 40 | BRCM_CLUSTER_COUNT + \ |
| 41 | PLATFORM_CORE_COUNT) |
| 42 | |
| 43 | #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 |
| 44 | |
| 45 | /* TBD-STINGRAY */ |
| 46 | #define CACHE_WRITEBACK_SHIFT 6 |
| 47 | /* |
| 48 | * Some data must be aligned on the biggest cache line size in the platform. |
| 49 | * This is known only to the platform as it might have a combination of |
| 50 | * integrated and external caches. |
| 51 | */ |
| 52 | #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) |
| 53 | |
| 54 | /* TBD-STINGRAY */ |
| 55 | #define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL1 |
| 56 | |
| 57 | #define BL1_PLATFORM_STACK_SIZE 0x3300 |
| 58 | #define BL2_PLATFORM_STACK_SIZE 0xc000 |
| 59 | #define BL11_PLATFORM_STACK_SIZE 0x2b00 |
| 60 | #define DEFAULT_PLATFORM_STACK_SIZE 0x400 |
| 61 | #if IMAGE_BL1 |
| 62 | # define PLATFORM_STACK_SIZE BL1_PLATFORM_STACK_SIZE |
| 63 | #else |
| 64 | #if IMAGE_BL2 |
| 65 | #ifdef USE_BL1_RW |
| 66 | # define PLATFORM_STACK_SIZE BL2_PLATFORM_STACK_SIZE |
| 67 | #else |
| 68 | # define PLATFORM_STACK_SIZE BL1_PLATFORM_STACK_SIZE |
| 69 | #endif |
| 70 | #else |
| 71 | #if IMAGE_BL11 |
| 72 | # define PLATFORM_STACK_SIZE BL11_PLATFORM_STACK_SIZE |
| 73 | #else |
| 74 | # define PLATFORM_STACK_SIZE DEFAULT_PLATFORM_STACK_SIZE |
| 75 | #endif |
| 76 | #endif |
| 77 | #endif |
| 78 | |
| 79 | #define PLAT_BRCM_TRUSTED_SRAM_BASE 0x66D00000 |
| 80 | #define PLAT_BRCM_TRUSTED_SRAM_SIZE 0x00040000 |
| 81 | |
| 82 | #ifdef RUN_BL1_FROM_QSPI /* BL1 XIP from QSPI */ |
| 83 | # define PLAT_BRCM_TRUSTED_ROM_BASE QSPI_BASE_ADDR |
| 84 | #elif RUN_BL1_FROM_NAND /* BL1 XIP from NAND */ |
| 85 | # define PLAT_BRCM_TRUSTED_ROM_BASE NAND_BASE_ADDR |
| 86 | #else /* BL1 executed in ROM */ |
| 87 | # define PLAT_BRCM_TRUSTED_ROM_BASE ROM_BASE_ADDR |
| 88 | #endif |
| 89 | #define PLAT_BRCM_TRUSTED_ROM_SIZE 0x00040000 |
| 90 | |
| 91 | /******************************************************************************* |
| 92 | * BL1 specific defines. |
| 93 | ******************************************************************************/ |
| 94 | #define BL1_RO_BASE PLAT_BRCM_TRUSTED_ROM_BASE |
| 95 | #define BL1_RO_LIMIT (PLAT_BRCM_TRUSTED_ROM_BASE \ |
| 96 | + PLAT_BRCM_TRUSTED_ROM_SIZE) |
| 97 | |
| 98 | /* |
| 99 | * Put BL1 RW at the beginning of the Trusted SRAM. |
| 100 | */ |
| 101 | #define BL1_RW_BASE (BRCM_BL_RAM_BASE) |
| 102 | #define BL1_RW_LIMIT (BL1_RW_BASE + 0x12000) |
| 103 | |
| 104 | #define BL11_RW_BASE BL1_RW_LIMIT |
| 105 | #define BL11_RW_LIMIT (PLAT_BRCM_TRUSTED_SRAM_BASE + \ |
| 106 | PLAT_BRCM_TRUSTED_SRAM_SIZE) |
| 107 | |
| 108 | /******************************************************************************* |
| 109 | * BL2 specific defines. |
| 110 | ******************************************************************************/ |
| 111 | #if RUN_BL2_FROM_QSPI /* BL2 XIP from QSPI */ |
| 112 | #define BL2_BASE QSPI_BASE_ADDR |
| 113 | #define BL2_LIMIT (BL2_BASE + 0x40000) |
| 114 | #define BL2_RW_BASE BL1_RW_LIMIT |
| 115 | #define BL2_RW_LIMIT (PLAT_BRCM_TRUSTED_SRAM_BASE + \ |
| 116 | PLAT_BRCM_TRUSTED_SRAM_SIZE) |
| 117 | #elif RUN_BL2_FROM_NAND /* BL2 XIP from NAND */ |
| 118 | #define BL2_BASE NAND_BASE_ADDR |
| 119 | #define BL2_LIMIT (BL2_BASE + 0x40000) |
| 120 | #define BL2_RW_BASE BL1_RW_LIMIT |
| 121 | #define BL2_RW_LIMIT (PLAT_BRCM_TRUSTED_SRAM_BASE + \ |
| 122 | PLAT_BRCM_TRUSTED_SRAM_SIZE) |
| 123 | #else |
| 124 | #define BL2_BASE (BL1_RW_LIMIT + PAGE_SIZE) |
| 125 | #define BL2_LIMIT (BRCM_BL_RAM_BASE + BRCM_BL_RAM_SIZE) |
| 126 | #endif |
| 127 | |
| 128 | /* |
| 129 | * BL1 persistent area in internal SRAM |
| 130 | * This area will increase as more features gets into BL1 |
| 131 | */ |
| 132 | #define BL1_PERSISTENT_DATA_SIZE 0x2000 |
| 133 | |
| 134 | /* To reduce BL2 runtime footprint, we can re-use some BL1_RW area */ |
| 135 | #define BL1_RW_RECLAIM_BASE (PLAT_BRCM_TRUSTED_SRAM_BASE + \ |
| 136 | BL1_PERSISTENT_DATA_SIZE) |
| 137 | |
| 138 | /******************************************************************************* |
| 139 | * BL3-1 specific defines. |
| 140 | ******************************************************************************/ |
| 141 | /* Max Size of BL31 (in DRAM) */ |
| 142 | #define PLAT_BRCM_MAX_BL31_SIZE 0x30000 |
| 143 | |
| 144 | #ifdef USE_DDR |
| 145 | #define BL31_BASE BRCM_AP_TZC_DRAM1_BASE |
| 146 | |
| 147 | #define BL31_LIMIT (BRCM_AP_TZC_DRAM1_BASE + \ |
| 148 | PLAT_BRCM_MAX_BL31_SIZE) |
| 149 | #else |
| 150 | /* Put BL3-1 at the end of external on-board SRAM connected as NOR flash */ |
| 151 | #define BL31_BASE (NOR_BASE_ADDR + NOR_SIZE - \ |
| 152 | PLAT_BRCM_MAX_BL31_SIZE) |
| 153 | |
| 154 | #define BL31_LIMIT (NOR_BASE_ADDR + NOR_SIZE) |
| 155 | #endif |
| 156 | |
| 157 | #define SECURE_DDR_END_ADDRESS BL31_LIMIT |
| 158 | |
| 159 | #ifdef NEED_SCP_BL2 |
| 160 | #define SCP_BL2_BASE BL31_BASE |
| 161 | #define PLAT_MAX_SCP_BL2_SIZE 0x9000 |
| 162 | #define PLAT_SCP_COM_SHARED_MEM_BASE (CRMU_SHARED_SRAM_BASE) |
| 163 | /* dummy defined */ |
| 164 | #define PLAT_BRCM_MHU_BASE 0x0 |
| 165 | #endif |
| 166 | |
| 167 | #define SECONDARY_CPU_SPIN_BASE_ADDR BRCM_SHARED_RAM_BASE |
| 168 | |
| 169 | /* Generic system timer counter frequency */ |
| 170 | #ifndef SYSCNT_FREQ |
| 171 | #define SYSCNT_FREQ (125 * 1000 * 1000) |
| 172 | #endif |
| 173 | |
| 174 | /* |
| 175 | * Enable the BL32 definitions, only when optee os is selected as secure |
| 176 | * payload (BL32). |
| 177 | */ |
| 178 | #ifdef SPD_opteed |
| 179 | /* |
| 180 | * Reserved Memory Map : SHMEM & TZDRAM. |
| 181 | * |
| 182 | * +--------+----------+ 0x8D000000 |
| 183 | * | SHMEM (NS) | 16MB |
| 184 | * +-------------------+ 0x8E000000 |
| 185 | * | | TEE_RAM(S)| 4MB |
| 186 | * + TZDRAM +----------+ 0x8E400000 |
| 187 | * | | TA_RAM(S) | 12MB |
| 188 | * +-------------------+ 0x8F000000 |
| 189 | * | BL31 Binary (S) | 192KB |
| 190 | * +-------------------+ 0x8F030000 |
| 191 | */ |
| 192 | |
| 193 | #define BL32_VA_SIZE (4 * 1024 * 1024) |
| 194 | #define BL32_BASE (0x8E000000) |
| 195 | #define BL32_LIMIT (BL32_BASE + BL32_VA_SIZE) |
| 196 | #define TSP_SEC_MEM_BASE BL32_BASE |
| 197 | #define TSP_SEC_MEM_SIZE BL32_VA_SIZE |
| 198 | #endif |
| 199 | |
| 200 | #ifdef SPD_opteed |
| 201 | #define SECURE_DDR_BASE_ADDRESS BL32_BASE |
| 202 | #else |
| 203 | #define SECURE_DDR_BASE_ADDRESS BL31_BASE |
| 204 | #endif |
| 205 | /******************************************************************************* |
| 206 | * Platform specific page table and MMU setup constants |
| 207 | ******************************************************************************/ |
| 208 | |
| 209 | #define MAX_XLAT_TABLES 7 |
| 210 | |
| 211 | #define PLAT_BRCM_MMAP_ENTRIES 10 |
| 212 | |
| 213 | #define MAX_MMAP_REGIONS (PLAT_BRCM_MMAP_ENTRIES + \ |
| 214 | BRCM_BL_REGIONS) |
| 215 | |
| 216 | #ifdef USE_DDR |
| 217 | #ifdef BL33_OVERRIDE_LOAD_ADDR |
| 218 | #define PLAT_BRCM_NS_IMAGE_OFFSET BL33_OVERRIDE_LOAD_ADDR |
| 219 | #else |
| 220 | /* |
| 221 | * BL3-3 image starting offset. |
| 222 | * Putting start of DRAM as of now. |
| 223 | */ |
| 224 | #define PLAT_BRCM_NS_IMAGE_OFFSET 0x80000000 |
| 225 | #endif /* BL33_OVERRIDE_LOAD_ADDR */ |
| 226 | #else |
| 227 | /* |
| 228 | * BL3-3 image starting offset. |
| 229 | * Putting start of external on-board SRAM as of now. |
| 230 | */ |
| 231 | #define PLAT_BRCM_NS_IMAGE_OFFSET NOR_BASE_ADDR |
| 232 | #endif /* USE_DDR */ |
| 233 | /****************************************************************************** |
| 234 | * Required platform porting definitions common to all BRCM platforms |
| 235 | *****************************************************************************/ |
| 236 | |
| 237 | #define MAX_IO_DEVICES 5 |
| 238 | #define MAX_IO_HANDLES 6 |
| 239 | |
| 240 | #define PRIMARY_CPU 0 |
| 241 | |
| 242 | /* GIC Parameter */ |
| 243 | #define PLAT_BRCM_GICD_BASE GIC500_BASE |
| 244 | #define PLAT_BRCM_GICR_BASE (GIC500_BASE + 0x200000) |
| 245 | |
| 246 | /* Define secure interrupt as per Group here */ |
| 247 | #define PLAT_BRCM_G1S_IRQ_PROPS(grp) \ |
| 248 | INTR_PROP_DESC(BRCM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, (grp), \ |
| 249 | GIC_INTR_CFG_EDGE), \ |
| 250 | INTR_PROP_DESC(BRCM_IRQ_SEC_SPI_0, GIC_HIGHEST_SEC_PRIORITY, (grp), \ |
| 251 | GIC_INTR_CFG_EDGE) |
| 252 | |
| 253 | #define PLAT_BRCM_G0_IRQ_PROPS(grp) \ |
| 254 | INTR_PROP_DESC(BRCM_IRQ_SEC_SGI_0, PLAT_SDEI_NORMAL_PRI, (grp), \ |
| 255 | GIC_INTR_CFG_EDGE), \ |
| 256 | |
| 257 | /* |
| 258 | *CCN 502 related constants. |
| 259 | */ |
| 260 | #define PLAT_BRCM_CLUSTER_COUNT 4 /* Number of RN-F Masters */ |
| 261 | #define PLAT_BRCM_CLUSTER_TO_CCN_ID_MAP CLUSTER0_NODE_ID, CLUSTER1_NODE_ID, CLUSTER2_NODE_ID, CLUSTER3_NODE_ID |
| 262 | #define CCN_SIZE 0x1000000 |
| 263 | #define CLUSTER0_NODE_ID 1 |
| 264 | #define CLUSTER1_NODE_ID 7 |
| 265 | #define CLUSTER2_NODE_ID 9 |
| 266 | #define CLUSTER3_NODE_ID 15 |
| 267 | |
| 268 | #endif |