blob: a9b1d8f0988324a2edfca78dfce11c01ccc1c9a4 [file] [log] [blame]
Etienne Carriere911de8c2018-02-02 13:23:22 +01001/*
2 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <asm_macros.S>
9#include <assert_macros.S>
10#include <platform_def.h>
11
12 .globl plat_my_core_pos
13 .globl plat_get_my_entrypoint
14 .globl platform_mem_init
15 .globl plat_qemu_calc_core_pos
16 .globl plat_crash_console_init
17 .globl plat_crash_console_putc
18 .globl plat_secondary_cold_boot_setup
19 .globl plat_get_my_entrypoint
20 .globl plat_is_my_cpu_primary
21
22
23func plat_my_core_pos
24 ldcopr r0, MPIDR
25 b plat_qemu_calc_core_pos
26endfunc plat_my_core_pos
27
28/*
29 * unsigned int plat_qemu_calc_core_pos(u_register_t mpidr);
30 * With this function: CorePos = (ClusterId * 4) + CoreId
31 */
32func plat_qemu_calc_core_pos
33 and r1, r0, #MPIDR_CPU_MASK
34 and r0, r0, #MPIDR_CLUSTER_MASK
35 add r0, r1, r0, LSR #6
36 bx lr
37endfunc plat_qemu_calc_core_pos
38
39 /* -----------------------------------------------------
40 * unsigned int plat_is_my_cpu_primary (void);
41 *
42 * Find out whether the current cpu is the primary
43 * cpu.
44 * -----------------------------------------------------
45 */
46func plat_is_my_cpu_primary
47 ldcopr r0, MPIDR
48 ldr r1, =(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
49 and r0, r1
50 cmp r0, #QEMU_PRIMARY_CPU
51 moveq r0, #1
52 movne r0, #0
53 bx lr
54endfunc plat_is_my_cpu_primary
55
56 /* -----------------------------------------------------
57 * void plat_secondary_cold_boot_setup (void);
58 *
59 * This function performs any platform specific actions
60 * needed for a secondary cpu after a cold reset e.g
61 * mark the cpu's presence, mechanism to place it in a
62 * holding pen etc.
63 * -----------------------------------------------------
64 */
65func plat_secondary_cold_boot_setup
66 /* Calculate address of our hold entry */
67 bl plat_my_core_pos
68 lsl r0, r0, #PLAT_QEMU_HOLD_ENTRY_SHIFT
69 mov_imm r2, PLAT_QEMU_HOLD_BASE
70
71 /* Wait until we have a go */
72poll_mailbox:
73 ldr r1, [r2, r0]
74 cmp r1, #0
75 beq 1f
76 mov_imm r0, PLAT_QEMU_TRUSTED_MAILBOX_BASE
77 ldr r1, [r0]
78 bx r1
791:
80 wfe
81 b poll_mailbox
82endfunc plat_secondary_cold_boot_setup
83
84func plat_get_my_entrypoint
85 /* TODO support warm boot */
86 mov r0, #0
87 bx lr
88endfunc plat_get_my_entrypoint
89
90func platform_mem_init
91 bx lr
92endfunc platform_mem_init
93
94 /* ---------------------------------------------
95 * int plat_crash_console_init(void)
96 * Function to initialize the crash console
97 * without a C Runtime to print crash report.
98 * Clobber list : x0, x1, x2
99 * ---------------------------------------------
100 */
101func plat_crash_console_init
102 mov_imm r0, PLAT_QEMU_CRASH_UART_BASE
103 mov_imm r1, PLAT_QEMU_CRASH_UART_CLK_IN_HZ
104 mov_imm r2, PLAT_QEMU_CONSOLE_BAUDRATE
105 b console_core_init
106endfunc plat_crash_console_init
107
108 /* ---------------------------------------------
109 * int plat_crash_console_putc(int c)
110 * Function to print a character on the crash
111 * console without a C Runtime.
112 * Clobber list : x1, x2
113 * ---------------------------------------------
114 */
115func plat_crash_console_putc
116 mov_imm r1, PLAT_QEMU_CRASH_UART_BASE
117 b console_core_putc
118endfunc plat_crash_console_putc
119